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Observer chevalier_noir
Observer
2,948 Views
Registered: ‎10-16-2017

Multi-driven net warning

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Hi all,

 

When I synthetise my design, I have a critical warning that says :

[Synth 8-3352] multi-driven net RPC_RWDS_OBUF with 1st driver pin 'design_1_i/rpc2_ctrl_io_0/inst/oddr_rds/q_reg__0/Q' ["/home/pierre/vivado/zc706_hyperbus_full/zc706_hyperbus_full.srcs/sources_1/imports/rtl/pads_sample/rpc2_ctrl_output_ddr.v":101]
[Synth 8-3352] multi-driven net RPC_RWDS_OBUF with 2nd driver pin 'design_1_i/rpc2_ctrl_io_0/inst/oddr_rds/q_reg/Q' ["/home/pierre/vivado/zc706_hyperbus_full/zc706_hyperbus_full.srcs/sources_1/imports/rtl/pads_sample/rpc2_ctrl_output_ddr.v":108]

Here are the verilog lines that are problematic :

 reg                  q;

   always @(posedge clk0 or posedge rst) begin
      if (rst)
        q <= INIT;
      else if (en)
        q <= d0;
   end

   always @(posedge clk1 or posedge rst) begin
      if (rst)
        q <= INIT;
      else if (en)
        q <= d1;
   end

Do you know where the problem could come from ?

 

Regards,

 

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1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
4,294 Views
Registered: ‎08-01-2008

Re: Multi-driven net warning

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yes its multi driven as you assign output q for two places .

 

   always @(posedge clk0 or posedge rst) begin
      if (rst)
        q <= INIT;
      else if (en)
        q <= d0;
   end

   always @(posedge clk1 or posedge rst) begin
      if (rst)
        q <= INIT;
      else if (en)
        q <= d1;
   end
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
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6 Replies
Xilinx Employee
Xilinx Employee
4,295 Views
Registered: ‎08-01-2008

Re: Multi-driven net warning

Jump to solution

yes its multi driven as you assign output q for two places .

 

   always @(posedge clk0 or posedge rst) begin
      if (rst)
        q <= INIT;
      else if (en)
        q <= d0;
   end

   always @(posedge clk1 or posedge rst) begin
      if (rst)
        q <= INIT;
      else if (en)
        q <= d1;
   end
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
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Scholar dpaul24
Scholar
2,932 Views
Registered: ‎08-07-2014

Re: Multi-driven net warning

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Do you know where the problem could come from ?

 

A basic rule of RTL coding is that you cannot drive a signal from more than one always block (process block in case of VHDL). The places where q is driven twice is shown in the above post.

 

However you can check the value of the signal inside any process.

 

I would suggest you to go through a good Verilog book/tutorial and then start coding.

 

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
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Observer chevalier_noir
Observer
2,913 Views
Registered: ‎10-16-2017

Re: Multi-driven net warning

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Ok thank you very much

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Historian
Historian
2,890 Views
Registered: ‎01-23-2009

Re: Multi-driven net warning

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It appears (both from the structure of the code, and the naming of the module) that you are trying to infer an output double data rate register. These cannot be inferred - they must be instantiated.

 

Avrum

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Observer chevalier_noir
Observer
2,632 Views
Registered: ‎10-16-2017

Re: Multi-driven net warning

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Hi,

 

How could I do this application without a multi driven net problem ?

 

Regards,

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Historian
Historian
2,591 Views
Registered: ‎01-23-2009

Re: Multi-driven net warning

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The only way to use an ODDR is to instantiate the cell directly (or use an IP that instantiates the cell directly).

 

To see a template for how to instantiate the ODDR for your technology you can use the language templates provided in the tool:

 

Tools -> Language Templates -> Verilog/VHDL -> Device Primitive Instantiation -> <device> -> I/O Components -> DDR Registers -> Output DDR Register (ODDR)

 

Of course, it goes without saying that this ODDR must drive an output port of the design only. There is no mechanism of generating/instantiating/using a double data rate register internal to the FPGA.

 

Avrum

 

 

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