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12-07-2017 02:53 AM
Hi all,
When I synthetise my design, I have a critical warning that says :
[Synth 8-3352] multi-driven net RPC_RWDS_OBUF with 1st driver pin 'design_1_i/rpc2_ctrl_io_0/inst/oddr_rds/q_reg__0/Q' ["/home/pierre/vivado/zc706_hyperbus_full/zc706_hyperbus_full.srcs/sources_1/imports/rtl/pads_sample/rpc2_ctrl_output_ddr.v":101] [Synth 8-3352] multi-driven net RPC_RWDS_OBUF with 2nd driver pin 'design_1_i/rpc2_ctrl_io_0/inst/oddr_rds/q_reg/Q' ["/home/pierre/vivado/zc706_hyperbus_full/zc706_hyperbus_full.srcs/sources_1/imports/rtl/pads_sample/rpc2_ctrl_output_ddr.v":108]
Here are the verilog lines that are problematic :
reg q; always @(posedge clk0 or posedge rst) begin if (rst) q <= INIT; else if (en) q <= d0; end always @(posedge clk1 or posedge rst) begin if (rst) q <= INIT; else if (en) q <= d1; end
Do you know where the problem could come from ?
Regards,
12-07-2017 03:02 AM - edited 12-07-2017 03:04 AM
yes its multi driven as you assign output q for two places .
always @(posedge clk0 or posedge rst) begin if (rst) q <= INIT; else if (en) q <= d0; end always @(posedge clk1 or posedge rst) begin if (rst) q <= INIT; else if (en) q <= d1; end
12-07-2017 03:02 AM - edited 12-07-2017 03:04 AM
yes its multi driven as you assign output q for two places .
always @(posedge clk0 or posedge rst) begin if (rst) q <= INIT; else if (en) q <= d0; end always @(posedge clk1 or posedge rst) begin if (rst) q <= INIT; else if (en) q <= d1; end
12-07-2017 03:30 AM - edited 12-07-2017 03:31 AM
Do you know where the problem could come from ?
A basic rule of RTL coding is that you cannot drive a signal from more than one always block (process block in case of VHDL). The places where q is driven twice is shown in the above post.
However you can check the value of the signal inside any process.
I would suggest you to go through a good Verilog book/tutorial and then start coding.
12-07-2017 04:35 AM
Ok thank you very much
12-07-2017 08:58 AM
It appears (both from the structure of the code, and the naming of the module) that you are trying to infer an output double data rate register. These cannot be inferred - they must be instantiated.
Avrum
01-16-2018 07:02 AM
Hi,
How could I do this application without a multi driven net problem ?
Regards,
01-20-2018 07:27 AM - edited 01-20-2018 07:28 AM
The only way to use an ODDR is to instantiate the cell directly (or use an IP that instantiates the cell directly).
To see a template for how to instantiate the ODDR for your technology you can use the language templates provided in the tool:
Tools -> Language Templates -> Verilog/VHDL -> Device Primitive Instantiation -> <device> -> I/O Components -> DDR Registers -> Output DDR Register (ODDR)
Of course, it goes without saying that this ODDR must drive an output port of the design only. There is no mechanism of generating/instantiating/using a double data rate register internal to the FPGA.
Avrum