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djmpap
Observer
Observer
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Registered: ‎07-22-2013

[Netlist 29-356] Non-native (unplaceable) cell 'my_inst' of type 'IBUF' found in post-transformed netlist.

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I am running 2019.1 targeting an Ultrazed-EG SOM which is an XCZU3EG-1SFVA625.  I've compiled the design successfully several times, but today started to get these errors:

  • [Netlist 29-356] Non-native (unplaceable) cell 'B40_MIO_SYNC_IBUF_inst' of type 'IBUF' found in post-transformed netlist.
  • [Netlist 29-356] Non-native (unplaceable) cell 'B40_NODE_ID_IBUF[0]_inst' of type 'IBUF' found in post-transformed netlist.
  • [Netlist 29-356] Non-native (unplaceable) cell 'B40_NODE_ID_IBUF[1]_inst' of type 'IBUF' found in post-transformed netlist.

[more deleted]

  • [Shape Builder 18-121] Failed to get a compatible bel element for instance B40_MIO_SYNC_IBUF_inst of type IBUF.
  • [Shape Builder 18-121] Failed to get a compatible bel element for instance B40_NODE_ID_IBUF[0]_inst of type IBUF.
  • [Shape Builder 18-121] Failed to get a compatible bel element for instance B40_NODE_ID_IBUF[1]_inst of type IBUF.

These occur post-synthesis.  It seems to be telling me that an IBUF is not a legal cell.  I do not have instantiated IBUFs in the design - I assume that these errors are from the post-synthesized netlist.  The sites are all legal sites and I've checked the IO_STANDARDs which seem to match.  And as I've said, I've built this design with these same constraints several times without these errors.

A couple of experiments that I've tried: Since they are all inputs, I tried adding the PIO_DIRECTION to these inputs - this didn't make any difference.  I also opened up the package view and tried to drag the I/O port to the appropriate pin.  As I go to drop it on the pin, a pop-up window states "Unknown instance type IBUF".

Any help would be appreciated.

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djmpap
Observer
Observer
967 Views
Registered: ‎07-22-2013

Version 2019.2 seems to correct this problem, but this is a Ultrascale+ Zynq design and 2019.2 only exports to Vitis for software development which would involve much at this stage in our design process (prototyping).  I found that 2019.1 SP3 also fixes this issue.

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djmpap
Observer
Observer
1,183 Views
Registered: ‎07-22-2013

Update: I created a new project, imported the source and constraint files and this worked, so a workaround is available.

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viviany
Xilinx Employee
Xilinx Employee
1,161 Views
Registered: ‎05-14-2008

Looks like something was wrong in the old project that it didn't recognize IBUF primitive.

Building a new project is a workaround we usually do for this kind of problems.

-Vivian

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djmpap
Observer
Observer
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Registered: ‎07-22-2013

It seems that the problem came back on the second build, so this workaround really isn't a workaround. I shouldn't have to build a new project every hour - especially since it takes over an hour to do.

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viviany
Xilinx Employee
Xilinx Employee
1,091 Views
Registered: ‎05-14-2008

So the issue does not occur in a new project at the beginning.

But will occur after a while?

Is there any obvious trigger for the error to occur?

Can you provide your project for us to reproduce the issue?

Which Vivado version are you using? Can you try the latest 2020.1?

-vivian

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Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
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djmpap
Observer
Observer
1,071 Views
Registered: ‎07-22-2013

I've moved on to 2019.2 and at least for the few times I've tried it, it seems to be fixed.  

viviany
Xilinx Employee
Xilinx Employee
1,026 Views
Registered: ‎05-14-2008

Please mark an answer as solution to close this thread.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
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djmpap
Observer
Observer
968 Views
Registered: ‎07-22-2013

Version 2019.2 seems to correct this problem, but this is a Ultrascale+ Zynq design and 2019.2 only exports to Vitis for software development which would involve much at this stage in our design process (prototyping).  I found that 2019.1 SP3 also fixes this issue.

View solution in original post

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