03-21-2019 01:22 AM
I created a new IP using create and package new IP. In the custom IP i used axi master and slave peripheral and also some user written verilog files and block rams. Then i packaged my ip and used it in the block diagram with the zynq processor. And then i synthesized and implement my design. But in both the synthesized and implement design i cannot find the generated netlist for my user written verilog files and some block rams. Vivado is somehow ignoring that files and block rams.
I am using vivado 2018.3
03-21-2019 01:48 AM
Hi @nomi_070 ,
It might got trimmed during synthesis!!
You will find the warning/critical warnings/info. messages in synthesis log file if any logic/signal/net get trimmed/removed or not. Hence, do a check on it.
And then change your RTL according to the messages.
03-25-2019 12:11 AM
03-26-2019 08:57 AM
I have made many versions of my project during the development phase. So finaly i used a previous version of my project in which netlist are generating fine.
But i could not find the root cause of the problem. I even made a new project but the problem still remains the same.