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Visitor
Visitor
352 Views
Registered: ‎12-27-2018

Netlist not found in synthesis and implemetation

I created a new IP using create and package new IP. In the custom IP i used axi master and slave peripheral and also some user written verilog files and block rams. Then i packaged my ip and used it in the block diagram with the zynq processor. And then i synthesized and implement my design. But in both the synthesized and implement design i cannot find the generated netlist for my user written verilog files and some block rams. Vivado is somehow ignoring that files and block rams.

I am using vivado 2018.3

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Moderator
Moderator
343 Views
Registered: ‎03-16-2017

Re: Netlist not found in synthesis and implemetation

Hi @nomi_070 ,

It might got trimmed during synthesis!!

You will find the warning/critical warnings/info. messages in synthesis log file if any logic/signal/net get trimmed/removed or not. Hence, do a check on it. 

And then change your RTL according to the messages. 

Regards,
hemangd

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Moderator
Moderator
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Registered: ‎03-16-2017

Re: Netlist not found in synthesis and implemetation

Hi @nomi_070 ,

This topic is still open. 

Can you please update on it?

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Visitor
Visitor
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Registered: ‎12-27-2018

Re: Netlist not found in synthesis and implemetation

I have made many versions of my project during the development phase. So finaly i used a previous version of my project in which netlist are generating fine.

But i could not find the root cause of the problem. I even made a new project but the problem still remains the same.

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