cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
1,499 Views
Registered: ‎04-11-2017

Netlist shows the path Which is not part of the original RTL

I have a clocks block in one subsystem and from that module the clocks are assigned to various IP's in the sub system. But after synthesis the netlist shows that the clock from the specific subsystem goes to the top of the design followed by a BUFG and again comes back into the sub system. I have no such path in my design. Why is the tool making this paths which might effect the functionality of the design ?

Tags (1)
0 Kudos
Reply
7 Replies
Moderator
Moderator
1,476 Views
Registered: ‎07-21-2014

@anjaneyulu.challa9

 

What is the hierarchy setting you are using for synthesis?

 

I believe you are using 'rebuilt' where the tool will flatten the hierarchy then optimize and then netlist will be rebuilt again. Can you use KEEP_HIERARCHY or 'none' and let us know the results?

 

Thanks

Anusheel 

0 Kudos
Reply
1,467 Views
Registered: ‎04-11-2017

@anusheel We are seeing some other issues in implementation while using the flatten_hierarchy to none

0 Kudos
Reply
Moderator
Moderator
1,456 Views
Registered: ‎07-21-2014

@anjaneyulu.challa9

 

Feel free to post your queries in implementation board if you are seeing any issues. Regarding the net/cell names, I believe the changes occurred due to flattening of hierarchy.

 

Thanks

Anusheel 

0 Kudos
Reply
1,447 Views
Registered: ‎04-11-2017

@anusheel Ideally the netlist should show up something which is something near to the RTL logic. If it shows something which is not in the  design them debugging those issues is a problem right ? Moreover this things add up some delays in the design and cause some timing issues with higher speeds

0 Kudos
Reply
Moderator
Moderator
1,443 Views
Registered: ‎07-21-2014

@anjaneyulu.challa9

 

By using 'rebuilt' you are allowing the tool to perform cross boundary optimization and hence the netlist is different than what you see in RTL. You can select the preserve hierarchy option available in the tool Or use DONT_TOUCH/KEEP_HIERARCHY attribute to block tool from performing such optimizations.

 

>>Moreover this things add up some delays in the design and cause some timing issues with higher speeds

Can you elaborate the issue and show us the schematic?

 

Thanks

Anusheel 

0 Kudos
Reply
1,405 Views
Registered: ‎04-11-2017

ERROR: [Opt 31-67] Problem: A LUT3 cell in the design is missing a connection on input pin I1, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic.

 

This is the ERROR i get when I set flatten hierarchy to none

0 Kudos
Reply
Moderator
Moderator
1,400 Views
Registered: ‎03-16-2017

Hi @anjaneyulu.challa9,

 

Set a DONT_TOUCH property on the LUT3 driving the LUT mentioned in the error. This can be found from an open synthesized design. 

 

set_property DONT_TOUCH true [get_cells <lut3_name>]

 

Regards,

hemangd

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
0 Kudos
Reply