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franzforstmayr
Contributor
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Registered: ‎09-20-2017

Not a valid clock source [BD 41-758] when using clocking wizard

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Hi,

I've attached my design of a synchronizer used for sysref generation for the rf-dataconverter ip. This design was working well in Vivado 2018.2, but I'm getting this error in Vivado 2019.1:

[BD 41-758] The following clock pins are not connected to a valid clock source:
/hier_0/xpm_cdc_single_w_0/dest_clk
/hier_0/clk_wiz_0/clk_in1
/hier_0/clk_wiz_1/clk_in1

How to proceed in my case?

Regards Franz

Screenshot from 2019-06-25 10-49-30.png
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franzforstmayr
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Registered: ‎09-20-2017

I finally fixed the issue by deleting the whole hierarchy and created it again. 

No matter, thanks for your effort!

View solution in original post

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dror_m
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Registered: ‎06-19-2019
try connecting the IBUF_OUT of util_ds_buf_1 to the clk_in1 of clk_wiz_0 and clk_out1 to xpm_cdc_single_w_2. id u need different frequency then the current the add another clock output.
for the xpm_cdc_single_w_0 it is clear that u didn't connect a valid clock (the output from xpm_cdc_single_w_2)
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franzforstmayr
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Registered: ‎09-20-2017
> for the xpm_cdc_single_w_0 it is clear that u didn't connect a valid clock (the output from xpm_cdc_single_w_2)
It's not the src_clk complaining, but the dest_clk, which is coming from the clk_wizard.
I'll have to try the other things you mentioned.
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dror_m
Observer
Observer
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Registered: ‎06-19-2019
sorry, thought it was src_clk.
u can try to put BUFG on the clk_out1
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franzforstmayr
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Contributor
1,693 Views
Registered: ‎09-20-2017

I finally fixed the issue by deleting the whole hierarchy and created it again. 

No matter, thanks for your effort!

View solution in original post

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