06-25-2019 01:56 AM
I've attached my design of a synchronizer used for sysref generation for the rf-dataconverter ip. This design was working well in Vivado 2018.2, but I'm getting this error in Vivado 2019.1:
[BD 41-758] The following clock pins are not connected to a valid clock source:
How to proceed in my case?
06-25-2019 02:49 AM
06-25-2019 03:51 AM