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muneet
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Registered: ‎06-18-2018

Out of Context Implementation for Design with Transceiver Pins

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I am using Kintex-7 FPGA and it has 500 Pins. My modular top file has 900 Pins and its the internal module of a top level design. I want to do its timing analysis. So, I am trying to do its implementation using Out of Context Mode. But in the Place Design Phase the tools throws errors for Transceiver Clocking Pins.

[DRC REQP-1619] IBUFDS_GTE2_driven_by_IBUF: IBUFDS_GTE2 clocking_wrapper_inst_when_bufds_is_true.arinc818_clocking_module/buf_ds_instantiation.ibufds_instq0_gtx_ref_clk pins I and IB should be driven by IBUFs. [Which is expected as the IBUFDS_GTE2 inputs must be driven by the Input Buffers]

Is there any way to avoid this and do implementation with the current modular top file?

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rshekhaw
Xilinx Employee
Xilinx Employee
945 Views
Registered: ‎05-22-2018

Hi @muneet ,

The primitive IBUFDS_GTE2 needs IBUF inserted on the I and IB pins for it to be properly placed. In your case as you have set the module as OOC, the synthesis will not insert IBUF on the module ports and hence the error. You need to instantiate IBUF in the code.

Please check this below forum post for detailed information:

https://forums.xilinx.com/t5/Implementation/Vivado-IBUFDS-GTE2-driven-by-IBUF/td-p/383187

Thanks,

Raj

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rshekhaw
Xilinx Employee
Xilinx Employee
946 Views
Registered: ‎05-22-2018

Hi @muneet ,

The primitive IBUFDS_GTE2 needs IBUF inserted on the I and IB pins for it to be properly placed. In your case as you have set the module as OOC, the synthesis will not insert IBUF on the module ports and hence the error. You need to instantiate IBUF in the code.

Please check this below forum post for detailed information:

https://forums.xilinx.com/t5/Implementation/Vivado-IBUFDS-GTE2-driven-by-IBUF/td-p/383187

Thanks,

Raj

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muneet
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Registered: ‎06-18-2018
Hi Raj,
Thanks for the quick solution. The implementation is completed using the instantiation of IBUFs.
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