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Visitor
Visitor
779 Views
Registered: ‎03-29-2020

Output signal

Using Vivado 2018.2 I want to make a program that receives an input signal and depending on its negative front I need to output an output signal.

- I create a custom AXI IP block;
- I added it in the design block;
- I wrote the testbench;
- I created the .xdc file;
- I exported the project;
- I created an application in the SDK.
The simulation works well but when I look at the output signal with the oscilloscope it remains in the last value it receives "0" or "1".

I don't know what's wrong.

The code I added in custom AXI IP:

-- Add user logic here

process (test)
begin
a <= '1';
b <= "0000";

if falling_edge(test) then
a <= '0' after 4 us, '1' after 13 us;
b(0) <= '1' after 3 us, '0' after 6 us;
b(1) <= '1' after 4 us, '0' after 8 us;
b(2) <= '1' after 5 us, '0' after 9 us;
b(3) <= '1' after 6 us, '0' after 10 us;
end if;

end process;

-- User logic ends

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16 Replies
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Adventurer
Adventurer
735 Views
Registered: ‎09-13-2018

Re: Output signal

Hi,

after X us is not synthesable construct - it works only in simulation. Ask yourself a question how does hardware can count time ?

You should imho get some vhdl online course or read book about design.
As a hint i would recommend using clock process that detects falling edge of test line, then use same clock for counting this x us

cheers n good luck

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Highlighted
Scholar
Scholar
728 Views
Registered: ‎08-07-2014

Re: Output signal

@gabby9753,

I don't know what's wrong.

That is why you must simulate the entire design before synthesis.

And since you have a custom AXI IP, I would recommend you to verify it using a AXI BFM before attaching it to your design.

 

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Highlighted
721 Views
Registered: ‎07-23-2019

Re: Output signal

 

a <= '0' after 4 us, '1' after 13 us;
b(0) <= '1' after 3 us, '0' after 6 us;
b(1) <= '1' after 4 us, '0' after 8 us;
b(2) <= '1' after 5 us, '0' after 9 us;
b(3) <= '1' after 6 us, '0' after 10 us;

after is not synthesizable, so you won't get what you want that way.

You need a state machine. The falling edge will trigger a state and you put your first outputs.

After some clocks, your 6 us, you jump to another state and set your second output

After some more clocks, an additional 2 us (to make 8 us from start) you change states again and set another output and so on.

Hopefully this points you in the right direction.

PS - actually, it could be simpler with just an FSM per output, with just 2 or 3 states (idle needed), depending on whether Mealy or Moore type.

 

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Visitor
Visitor
646 Views
Registered: ‎03-29-2020

Re: Output signal

If I write like that

----------------------------------------------------------------

-- Add user logic here

process
variable x : time;
variable y : time;
begin
a <= '1';
b <= "0000";

wait until rising_edge (S_AXI_ACLK);
x := now;
wait until falling_edge (S_AXI_ACLK);
y := now - x;

if falling_edge(test) then
a <= '0' after (400*y), '1' after (1300*y);
b(0) <= '1' after (300*y), '0' after (600*y);
b(1) <= '1' after (400*y), '0' after (800*y);
b(2) <= '1' after (500*y), '0' after (900*y);
b(3) <= '1' after (600*y), '0' after 1(000*y);
end if;

end process;

-- User logic ends

-----------------------------------------------------------------

(clock frequency) f = 50MHz   result   (period) T = 20ns   and  y = T/2 = 10ns

Is good now?

 

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Scholar
Scholar
635 Views
Registered: ‎08-01-2012

Re: Output signal

@gabby9753 

What are you trying to acheive? "After" keyword is for simulation only. NOW is also a simulation only function.

What hardware do you expect this code will produce?

Stop writing code, and draw a circuit diagram of your expect circuit. Then you can use that to work from when you write your code from scratch.

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Visitor
Visitor
622 Views
Registered: ‎03-29-2020

Re: Output signal

@richardhead 

But, this is good?

process
variable x : time;
variable y : time;
begin

wait until rising_edge (S_AXI_ACLK);
x := now;
wait until falling_edge (S_AXI_ACLK);
y := now - x;

end process;

Or is good only for simulation?

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Scholar
Scholar
603 Views
Registered: ‎08-01-2012

Re: Output signal

@gabby9753 

This is simulation only code:

1. You are using the NOW function - this is simulation only

2.  you have a process that waits for one edge and then another - this is NOT a synthesiable template

3. You're using the time type

So basically, nothing in your code is synthesisable.

Please DRAW your circuit ON PAPER.

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Visitor
Visitor
583 Views
Registered: ‎03-29-2020

Re: Output signal

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Scholar
Scholar
574 Views
Registered: ‎08-01-2012

Re: Output signal

@gabby9753 

Thats not a ciruict - thats a timing diagram.

You need a circuit that produces that timing diagram I assume.

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Highlighted
Visitor
Visitor
565 Views
Registered: ‎03-29-2020

Re: Output signal

@richardhead 

I know but, these signals I want to generate and I don't know how.
That's why I created an AXI4 IP and added my signals to it

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Scholar
Scholar
550 Views
Registered: ‎08-01-2012

Re: Output signal

@gabby9753 

What are you wanting us to do for you? Without a basic understanding of digital logic, you cannot do anything on FPGA.

Highlighted
Visitor
Visitor
535 Views
Registered: ‎03-29-2020

Re: Output signal

@richardhead 

I want to generate these signals by using vhdl, not using circuits. It's not possible to do this in vhdl?

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Highlighted
531 Views
Registered: ‎06-21-2017

Re: Output signal

VHDL is a hardware description language.  By describing the circuit in VHDL, you tell the synthesis tool how to build the hardware to do what you want.  FPGAs have registers (flip-flops) and Look Up Tables (LUTs) that can perform logic functions.  The code tells Vivado how to interconnect these and how to set up each LUT. 

Highlighted
525 Views
Registered: ‎07-23-2019

Re: Output signal

You need a state machine per output bit.

The falling edge will reset it and output will be o in that state

The SM will count cycles until it jumps to the next state where the output will be 1

The SM will count more cycles and jump to another state where the output will be 0 and will remain there until the next falling edge.

That's all. If what you want is detailed code, let me suggest that someone at freelancer.com may do it for you.

 

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Mentor
Mentor
511 Views
Registered: ‎04-26-2015

Re: Output signal


@gabby9753 wrote:

@richardhead 

I want to generate these signals by using vhdl, not using circuits. It's not possible to do this in vhdl?


You can do it using VHDL, as long as you don't try to run it on an FPGA (because the FPGA does use circuits). As long as you're happy to only run it in simulation, there are no problems.

 

If you want to run it on an FPGA, then as @richardhead wrote, you need to understand digital circuits. An FPGA is just a way of implementing a digital circuit without spending ages wiring the hardware by hand. You definitely need to understand what circuit you're asking the tools to build (via VHDL) to have any hope of getting the design working.

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Teacher
Teacher
468 Views
Registered: ‎07-09-2009

Re: Output signal

@gabby9753

So a few things here,

VHDL, is a simulation language,
you write it to wobble signal sup and down at various times, and to generate / check your design. That only runs on a processor, normally a desk top, and its not real time. Its how you have written the code above.

VHDL is also, if not primarily, a hardware description language. In an FPGA, you are describing registers, gates, to make counters, and other logic functions. The tools take your VHDL and make them into the logic your describing.

As such, in logic, if you have in your code, wait 5us,
you are not describing logic,
If you describe a counter, that counts off a 100 MHz clock, to a certain number, then wraps round to zero and keeps going, that is making you a period, in logic, that the tools can understand.

I suggest you get yourself a good book, I have no connection to them, but can I suggest,
http://freerangefactory.org/pdf/df344hdh4h8kjfh3500ft2/free_range_vhdl.pdf


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