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Explorer
Explorer
5,498 Views
Registered: ‎11-29-2015

Ported ISE project to Vivado. Now Get Multiple Driver Nets error

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I ported a VHDL FPGA project over to Vivado by creating a new project, importing copies of all of the required sources, and creating new IP cores where necessary for clock gens and block memories. Everything is fine except I've got Multiple Driver Nets errors for code that hasn't changed. I made sure to create the block memory with the same settings that were used in ISE.

 

[DRC 23-20] Rule violation (MDRV-1) Multiple Driver Nets - Net
IMAGE_PROCESSOR/blob_detector1_inst/rect_ram_inst/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/doutb[0] has multiple drivers: IMAGE_PROCESSOR/blob_detector1_inst/window[upper_right_rect][index][0]_i_2__0/O, IMAGE_PROCESSOR/blob_detector1_inst/rect_ram_inst/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/doutb[0]_INST_0/O.

 

rect_ram_inst: entity work.blk_mem_gen_1
        port map (
            clka  => clk,
            ena   => rect_ram.enable_a,
            wea   => rect_ram.write_enable_a,
            addra => rect_ram.addr_a,
            dina  => rect_ram.data_in_a,
            clkb  => clk,
            enb   => rect_ram.enable_b,
            addrb => rect_ram.addr_b,
            doutb => rect_ram.data_out_b
        );

 

The rect_ram.data_out_b vector is only ever read so I don't understand why I'm getting this error.

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Explorer
Explorer
8,158 Views
Registered: ‎11-29-2015

Re: Ported ISE project to Vivado. Now Get Multiple Driver Nets error

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I solved the issue. There was logic that set the data out signal of one of the simple two-port memory entities to (others => 'Z') when certain conditions were met. Regardless of whether that should or shouldn't be done that way, ISE handled it just fine, without issue. For some crazy, crazy, crazy reason the people that worked on Vivado didn't just take what was working fine in ISE and improve upon it. For some super insane reason it seems like they tried to re-implement what was already fine in ISE so now you get obscure, unhelpful errors for no good reason. Thanks.

 

I'm currently working on another random, shouldn't-be-there issue where Vivado takes a simple boolean variable, somehow breaks it up into a std_logic_vector, uses a DSP for it for no good reason and then throws errors about it. Again, the logic was fine in ISE. Thanks Vivado!

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11 Replies
Moderator
Moderator
5,488 Views
Registered: ‎01-16-2013

Re: Ported ISE project to Vivado. Now Get Multiple Driver Nets error

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@david12341234,

 

Open the elaborated design and check the connections of nets displayed in error message are actually multidriven. 

 

Check the similar forum threads:

https://forums.xilinx.com/t5/Synthesis/Drc-23-20/td-p/572067

 

--Syed

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Explorer
Explorer
5,457 Views
Registered: ‎11-29-2015

Re: Ported ISE project to Vivado. Now Get Multiple Driver Nets error

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Shown below are the signals in question. Looks like they are multidriven like Vivado says. That is no surprise. Now, getting back to the actual question, the issue is that they are not supposed to be, I didn't make them that way and they were fine in ISE. So to get back on track and reiterate the original question, why is this exact, unmodified code fine in ISE but not in Vivado?

 

Untitled.png

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Xilinx Employee
Xilinx Employee
5,433 Views
Registered: ‎04-16-2012

Re: Ported ISE project to Vivado. Now Get Multiple Driver Nets error

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Hi @david12341234

 

Which version of Vivado are you using?

Try setting the -flatten_hierarchy to none and see whether you encounter the multi-driven issue.

 

Thanks,

Vinay

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

Re: Ported ISE project to Vivado. Now Get Multiple Driver Nets error

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Can you please share complete project . AS per the above instant you should not get multiple driver error. I think root cause of error somewhere else
Thanks and Regards
Balkrishan
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Moderator
Moderator
5,416 Views
Registered: ‎07-21-2014

Re: Ported ISE project to Vivado. Now Get Multiple Driver Nets error

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@david12341234

 

Are you using generate block to infer the logic(FFs)? We have seen few issues with the generate block resulting in incorrect multi-driver issue. These issues are fixed in 2017.1 and as a work around you need to modify the RTL.

 

Thanks,
Anusheel
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Explorer
Explorer
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Registered: ‎11-29-2015

Re: Ported ISE project to Vivado. Now Get Multiple Driver Nets error

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v2016.3 (64-bit)

I set -flatten_hierarchy to none but still got the error.

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Explorer
Explorer
5,397 Views
Registered: ‎11-29-2015

Re: Ported ISE project to Vivado. Now Get Multiple Driver Nets error

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No. I literally copied the relevant VHDL files from the ISE project to the new Vivado project and then generated new IP of the clock generators and block memories. I suspect that there is something about the new block memory that has created this error. How would I get more insight into what is going on?

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Explorer
Explorer
5,377 Views
Registered: ‎11-29-2015

Re: Ported ISE project to Vivado. Now Get Multiple Driver Nets error

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Another error that may be related is the fact that Vivado never seems to recognize the block memories that were generated. In the editor it complains that they don't exist but during synthesis it doesn't complain that they don't exist but it instead gives about 100 critical synthesis warnings like this one:

[Synth 8-3352] multi-driven net IMAGE_PROCESSOR/blob_detector2_inst/row_label_ram[data_out_b][12] with 2nd driver pin 'IMAGE_PROCESSOR/blob_detector2_inst/row_label_ram_inst/doutb[12]'

 

Untitled.png

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Moderator
Moderator
5,347 Views
Registered: ‎07-21-2014

Re: Ported ISE project to Vivado. Now Get Multiple Driver Nets error

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@david12341234

 

From the above snapshot it looks like doutb should not result in multi-driver as the signal connected to it is different. Can you share the RTL file and .xci files of these memory IPs for us to reproduce the issue?

 

Thanks,
Anusheel
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Explorer
Explorer
3,607 Views
Registered: ‎11-29-2015

Re: Ported ISE project to Vivado. Now Get Multiple Driver Nets error

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I zipped up blk_mem_get_1 which is the ip causing this issue. If it is commented out, the project builds fine.

 

 

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Explorer
Explorer
8,159 Views
Registered: ‎11-29-2015

Re: Ported ISE project to Vivado. Now Get Multiple Driver Nets error

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I solved the issue. There was logic that set the data out signal of one of the simple two-port memory entities to (others => 'Z') when certain conditions were met. Regardless of whether that should or shouldn't be done that way, ISE handled it just fine, without issue. For some crazy, crazy, crazy reason the people that worked on Vivado didn't just take what was working fine in ISE and improve upon it. For some super insane reason it seems like they tried to re-implement what was already fine in ISE so now you get obscure, unhelpful errors for no good reason. Thanks.

 

I'm currently working on another random, shouldn't-be-there issue where Vivado takes a simple boolean variable, somehow breaks it up into a std_logic_vector, uses a DSP for it for no good reason and then throws errors about it. Again, the logic was fine in ISE. Thanks Vivado!

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