UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor asi_ka
Visitor
1,725 Views
Registered: ‎05-10-2017

Possible synthesis bug in Vivado 2018.1

I'm not sure how we report bugs, but here's the bug I see:

 

The if-else below works fine, but the case statement always goes to ST_1. This same case statement works fine in 2017.[2,3,4] and Questa sim.

 

 

				if (a)
					state <= ST_0;
				else if (b)
					state <= ST_1;

				case ({a,b})
					2'b10: state <= ST_0;
					2'b01: state <= ST_1;
				endcase
12 Replies
Scholar jmcclusk
Scholar
1,712 Views
Registered: ‎02-24-2014

Re: Possible synthesis bug in Vivado 2018.1

you should post a complete module as a test case, along with the conflicting results from the different tools..   Also, you need to verify that your test case fails in 2018.1, showing the result.    With a test case in hand, the mods will file a CR (Change Request) with the developers to get this fixed.  

Don't forget to close a thread when possible by accepting a post as a solution.
Visitor asi_ka
Visitor
1,698 Views
Registered: ‎05-10-2017

Re: Possible synthesis bug in Vivado 2018.1

thanks. Unfortunately I'm not at liberty of providing any more details due to company policy, and creating a separate test case would be too much time on my part.

0 Kudos
Scholar jmcclusk
Scholar
1,684 Views
Registered: ‎02-24-2014

Re: Possible synthesis bug in Vivado 2018.1

It's disappointing you don't have the time to create a minimal test case, if you really have found a bug.   Ask your manager if you can do it, because it's really important to fix synthesis tool bugs like this.

Don't forget to close a thread when possible by accepting a post as a solution.
0 Kudos
Voyager
Voyager
1,625 Views
Registered: ‎06-20-2017

Re: Possible synthesis bug in Vivado 2018.1

@asi_ka, how many bits does 'a' have?  What about 'b'?  It is obviously implied that it is 1 bit each, but I ask the question just in case there was a change in the declarations.

 

Mike
0 Kudos
Visitor asi_ka
Visitor
1,585 Views
Registered: ‎05-10-2017

Re: Possible synthesis bug in Vivado 2018.1

that's right, a and b are both 1-bit nets. state is a 3-bit register. This is all in an always_ff block.

 

Just to clarify, I only wrote the if-else equivalent because I got the wrong result from the case statement only in 2018.1. Nothing else in the module was changed.

0 Kudos
Visitor asi_ka
Visitor
1,582 Views
Registered: ‎05-10-2017

Re: Possible synthesis bug in Vivado 2018.1


@jmcclusk wrote:

It's disappointing you don't have the time to create a minimal test case, if you really have found a bug.   Ask your manager if you can do it, because it's really important to fix synthesis tool bugs like this.


I'd argue it's xilinx's job to take of these issues. It's a fairly easy to reproduce bug I'd say. Until they do I'm staying away from 2018.1

0 Kudos
Moderator
Moderator
1,566 Views
Registered: ‎05-31-2017

Re: Possible synthesis bug in Vivado 2018.1

Hi @asi_ka,

 

I have tried a simple test case as explained by you and I am not able to see any functionality issue i.e., it seems to be working fine. I have checked the Behaviour and Post synthesis Functional simulation and both seems to be functionally correct. Here I have attached the test case that I have used at my end. Please check it and let me know if I am missing something as per your scenario.

 

Thanks & Regards,
A.Shameer

 

Scholar jmcclusk
Scholar
1,546 Views
Registered: ‎02-24-2014

Re: Possible synthesis bug in Vivado 2018.1

It certainly is Xilinx's job to fix the bugs...  but they can't do that without test cases.   Reported bugs from vague descriptions are useless.   Right now, it's looking more like you have an error in your code.

Don't forget to close a thread when possible by accepting a post as a solution.
Observer aad_xlx
Observer
520 Views
Registered: ‎02-10-2019

Re: Possible synthesis bug in Vivado 2018.1

Similar to asi_ka (05-25-2018 7:02 AM) report:

> if-then-else works in Simulation and running on Device

> case works in Simulation, but is inverted when running on Device

Project attached in: CmodClocks.zip

------------------------------

clk_cntr_mhz_process : process (clk_cntr_mhz)
begin
    -- CORRECT IN SIMULATION AND ON DEVICE (xc7a15t)
    if(clk_cntr_mhz < CLK_MHZ_1) then
        clk_mhz <= '0';
    else
        clk_mhz <= '1';
    end if;
    CLKOUT <= clk_mhz;
    
    -- CORRECT in SIMULATION, INVERTED ON DEVICE (xc7a15t)
    --case clk_cntr_mhz is
    --    when CLK_MHZ_0 => clk_mhz <= '0';   -- drive to 0
    --    when CLK_MHZ_1 => clk_mhz <= '1';   -- drive to 1
    --    when others => null;
    --end case;
    --CLKOUT <= clk_mhz;
end process;

------------------------------

Simulation clock:

> add_force {/Clock1M1K/CLK} -radix bin {0 0ns} {1 41666ps} -repeat_every 83333ps

Running on this board: Cmod A7-15t (xc7a15tcpg236-1)

Please advise, thanks,

Dave

 

Tags (1)
0 Kudos
Moderator
Moderator
509 Views
Registered: ‎03-16-2017

Re: Possible synthesis bug in Vivado 2018.1

Hi @aad_xlx,

 

Create a new thread with your query and testcase so community can help you better. 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
Scholar drjohnsmith
Scholar
508 Views
Registered: ‎07-09-2009

Re: Possible synthesis bug in Vivado 2018.1

The commented out case depends upon CLK_MHZ_0 and CLK_MHZ_1, where as the working case only has CLK_MHZ_0

You dont secify what you have for CLK_MHZ_0 and CLK_MHZ_1, nore clk_cntr_mhz .

I'd normaly code this sort of signal on the lines of
clk_mhz <= '0' when CLK_MHZ_0 = clk_cnt_mhz else '1';

This is a more robust way of encoding,

Also, your missing the end process, but I assume thats a typo.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Observer aad_xlx
Observer
480 Views
Registered: ‎02-10-2019

Re: Possible synthesis bug in Vivado 2018.1

Thanks for comments.  I will rework example and submit as a new thread.

 

0 Kudos