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Visitor faizan.sayed
Visitor
955 Views
Registered: ‎04-05-2018

RTL and Gate Simulation mismatch(netlist generated with Vivado 2018.xx version)

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Hi,

we are seeing mismatches between RTL simulation and Gate simulations(Vivado generated netlists). lib_original_rtl.PNGoriginal_rtl.PNG
 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RTL and Gate sims are matching until line number 442, but they are mismatching from line number 446 onward. re_carr_offset_in is OK , but somehow , re_carr_offset_in_reg is mismatching in gatesims. We are seeing 0x3FE42 in RTL, whereas we are seeing 0xE42 in gatesims.  

We have tried the below fix, and tried synthesis and gatesims again, then it is working, both RTL and gatesims are matching.working_rtl_fix.PNG 

 

 

 

 

 

 

 

 

 

 

 

Can you please take a look?

 Regards,

Faizan Sayed

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1 Solution

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Visitor faizan.sayed
Visitor
711 Views
Registered: ‎04-05-2018

Re: RTL and Gate Simulation mismatch(netlist generated with Vivado 2018.xx version)

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Product Application Engineers fom Xilinx were able to reproduce this issue and considered this as BUG. they have file CR#1020580 and communicated that this will be solved in upcoming Xilinx Vivado 2019.1 and through pathches in 2018.x.

9 Replies
Scholar richardhead
Scholar
929 Views
Registered: ‎08-01-2012

Re: RTL and Gate Simulation mismatch(netlist generated with Vivado 2018.xx version)

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We cant take a look without you posting the code. A picture doesnt give us the whole code.

Where does clk_80 come from? is it a logic generated clock? does your design meet your timing requirements?

 

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Visitor faizan.sayed
Visitor
918 Views
Registered: ‎04-05-2018

Re: RTL and Gate Simulation mismatch(netlist generated with Vivado 2018.xx version)

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Hi @richardhead,

Yes the timings are met and this is our Legacy code proven on ASIC and Xilinx Virtex 6 FPGA with synopsis synplify pro synthesis + ISE 14.7 PnR earlier.
somehow this issue is reported if i use Vivado tool for Synthesis.

Note: i have migrated to ultra-scale(VCU108 platform now)  and i have also tried multiple strategies for synthesis in vivado.

From the Xilinx side, I am trying to understand what Vivado tool is doing and why this issue occurring in the Vivado 2018.x(tested with 2018 version) and if this is not reported then i would report this as Bug so that they correct in next revision.

Also the fix what is working, is not satisfactory... if we split the same signal in mapping, it works but when whole signals is mapped, errors are introduced (verified using RTL Simulation and Gate Simulation).

 

Regards,

Faizan Sayed 

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Scholar richardhead
Scholar
909 Views
Registered: ‎08-01-2012

Re: RTL and Gate Simulation mismatch(netlist generated with Vivado 2018.xx version)

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Without the code (or even better, a stand alone test case), it will be difficult for anyone to investigate.

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Visitor faizan.sayed
Visitor
878 Views
Registered: ‎04-05-2018

Re: RTL and Gate Simulation mismatch(netlist generated with Vivado 2018.xx version)

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@syedz Greetings!

will you be able to help us in this issue?

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Moderator
Moderator
866 Views
Registered: ‎07-21-2014

Re: RTL and Gate Simulation mismatch(netlist generated with Vivado 2018.xx version)

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@faizan.sayed

If you are able to find the signal resulting in incorrect logic, then try to apply DONT_TOUCH attribute to stop optimizations on/around that signal and see if functionality matches. 

If the attribute is not helpful for your issue, then please share the RTL file and testbench for us to debug.

Thanks
Anusheel 

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Visitor faizan.sayed
Visitor
854 Views
Registered: ‎04-05-2018

Re: RTL and Gate Simulation mismatch(netlist generated with Vivado 2018.xx version)

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sure @anusheel

ok I'll try with attribute dont_touch, and come back to you.

 

regards,

Faizan Sayed

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Visitor faizan.sayed
Visitor
766 Views
Registered: ‎04-05-2018

Re: RTL and Gate Simulation mismatch(netlist generated with Vivado 2018.xx version)

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Filed Service Request for this issue. SR#10456912

Product Application Engineers fom Xilinx arelooking into this issue.

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Visitor faizan.sayed
Visitor
712 Views
Registered: ‎04-05-2018

Re: RTL and Gate Simulation mismatch(netlist generated with Vivado 2018.xx version)

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Product Application Engineers fom Xilinx were able to reproduce this issue and considered this as BUG. they have file CR#1020580 and communicated that this will be solved in upcoming Xilinx Vivado 2019.1 and through pathches in 2018.x.

Explorer
Explorer
540 Views
Registered: ‎04-22-2015

Re: RTL and Gate Simulation mismatch(netlist generated with Vivado 2018.xx version)

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Can someone provide a link to the patch that resulted from this post?  I don't see it in AR#70644.

 

ken

 

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