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Participant
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Registered: ‎01-03-2018

Retiming option of Synthesis causes Synthesis failure - 2017.3.1

Hello,

 I am using Vivado 2017.3.1

As soon as enable Retiming in Synthesis, Synthesis fails with

TclStackFree: incorrect freePtr. Call out of sequence?

 

I cant upgrade to 2017.4 for some reason.I am going ahead without using the retiming option.

 

Thanks,

Sachin B

 

 

 

 

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Moderator
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Registered: ‎09-15-2016

Re: Retiming option of Synthesis causes Synthesis failure - 2017.3.1

Hi @sachinb_apt1,

 

Do you have a test-case that we can try?

 

Regards,
Prathik
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Participant
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Registered: ‎01-03-2018

Re: Retiming option of Synthesis causes Synthesis failure - 2017.3.1

I will try to give a test case. BTW i tried with 2017.4 as well. The same issue.
With 2017.4, an extra line printed in the runme.log file terminate called after throwing an instance of 'boost::exception_detail::clone_impl<boost::exception_detail::error_info_injector<boost::lock_error> >'
what(): boost: mutex lock failed in pthread_mutex_lock: Invalid argument

And there are 2 hs_err_pid*.log files generated. As far as i know, one one should be generated for a vivado crash. But here i got 2 of them.
Getting Retiming to work is extremely critical for us. Thanks
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Xilinx Employee
Xilinx Employee
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Registered: ‎02-16-2014

Re: Retiming option of Synthesis causes Synthesis failure - 2017.3.1

Hi @sachinb_apt1

 

Can you share vivado log and hs_err_pid* files to ahve a look?

It will be helpful if you can provide testcase to debug and provide you a workaround.

 

Thanks,

Manusha

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Registered: ‎01-03-2018

Re: Retiming option of Synthesis causes Synthesis failure - 2017.3.1

The attachment's hs_err_pid96778.log content type (text/x-log) does not match its file extension and has been removed.
The attachment's hs_err_pid96904.log content type (text/x-log) does not match its file extension and has been removed.
The attachment's runme.log content type (text/x-log) does not match its file extension and has been removed.

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Registered: ‎01-03-2018

Re: Retiming option of Synthesis causes Synthesis failure - 2017.3.1

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Re: Retiming option of Synthesis causes Synthesis failure - 2017.3.1

@pulim PFA files attached
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Re: Retiming option of Synthesis causes Synthesis failure - 2017.3.1

Is there a set_param in vivado, with which we can enable either the forward or backward register balancing like we would do them in ISE?

Well what i  really trying to get register balancing done using some micro level switches instead of a macro level retiming switch.

 

Also let me know if there is  way to apply retiming switch to certain module or instance?

Thanks,

Sachin B

 

 

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Participant
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Registered: ‎01-03-2018

Re: Retiming option of Synthesis causes Synthesis failure - 2017.3.1

Hi @pulim

  I suspect if a Combinatorial loop in GT logic is causing it.

The powergood signal generation in the GTY IP has a combinatorial loop. Which is mentioned in the runme log file i posted

See the snapshot attached.

 

Also let me know if there was a way to apply retiming to specific instance (and downstream) instead of entire design.

 

 

 

Combo_loop_in_GTY.png
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Xilinx Employee
Xilinx Employee
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Registered: ‎02-16-2014

Re: Retiming option of Synthesis causes Synthesis failure - 2017.3.1

Hi @sachinb_apt1

 

I did a quick search with the crash log but didnt find any known issues with similar log.

Can you share the project so that I can debug and report this to development team?

 

You can apply re-timing to specific module instead of entire design uisng block level synthesis.

Please check below.

set_property BLOCK_SYNTH.RETIMING 1 [get_cells  <instname>]

 

For more details on block level synthesis refer to chapter 3 in UG901.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug901-vivado-synthesis.pdf

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Participant
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Registered: ‎01-03-2018

Re: Retiming option of Synthesis causes Synthesis failure - 2017.3.1

Well with the block level

    Numbers of forward move = 0, and backward move = 0
    Numbers of forward move = 0, and backward move = 0
    Numbers of forward move = 0, and backward move = 0
    Numbers of forward move = 0, and backward move = 0
    Numbers of forward move = 0, and backward move = 0

 

So pretty much it passed the synthesis but did not do any register balancing.

And not sure what such messages in synth log

Total number of crtical paths = 0
    Total number of crtical paths = 0
    Total number of crtical paths = 0
    Total number of crtical paths = 0
    Total number of crtical paths = 0
    Total number of crtical paths = 0
    Total number of crtical paths = 0
    Total number of crtical paths = 0
    Total number of crtical paths = 0
    Total number of crtical paths = 0

 

During Synthesis the tool probably thinks there are no critical path and hence it did not do any register balancing.

However my post synthesis Negative Slack is -1.136 ns for the block i did the retiming with 16 levels of logic.

How did during synthesis/Retiming the tool saw not even a single path critical. Strange.

 

I tried creating a sharable testcase but it doesnt fail retiming in sub block level.

So cannot share the project.

 

Closing Comments for now--- Whether a tool does the retiming on some block or not, it should not crash the way it is.

 

 

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