SHREG_EXTRACT Not Honored?

[chsdkj]

It seems there was a post (not necessarily in this forum, and likely not recently) in which there was a comment that Austin had indicated that the SHREG_EXTRACT attribute was not always honored as expected.

For US/US+ devices, with the 2017.4 version of Vivado, are there possibly any situations where SHREG_EXTRACT may not be honored?  Specifically, for SHREG_EXTRACT = no, that SRLs might nevertheless be instantiated?

[austin]

There are three AR on the subject:

AR# 56498 - 2013.2 Vivado Synthesis - Why is shift register not inferred for an HDL design containing a clock enable in spite of setting the shreg_extract attribute to [AR] 2013.2 Vivado Synthesis does not infer a shift register for a HDL design containing a clock enable in spite of setting the shreg_extract attribute to ...	10/25/2013
AR# 53956 - Vivado Synthesis - How do you extract a shift register and how do you control the threshold of the register chain depth for SRL inference? [AR] ... The UG 901 will be updated in 2013.1 with respect to shreg_extract syntax and usage. ... (* shreg_extract = "{yes|no}, {true|false}" *) ...	10/25/2013
AR# 55334 - 2013.x Vivado Synthesis - Known Issues [AR] ... Vivado Synthesis - Why is shift register not inferred for a HDL design containing a clock enable in spite of setting the shreg_extract attribute to "yes ...

[chsdkj]

Austin,

Thanks for the links, however all relate to rather ancient versions of Vivado, and seem to typically involve situations where SRLs were not instantiated were they were actually desired.

As requested above: For US/US+ devices, with the 2017.4 version of Vivado, are there possibly any situations where SHREG_EXTRACT may not be honored?  Specifically, for SHREG_EXTRACT = no, that SRLs might nevertheless be instantiated?

[anusheel]

@chsdkj

The SHREG_EXTRACT attribute is for the inference of SRLs and not for the instantiation. Use of primitive will be treated differently.

Can you please share the RTL code which is not resulting in SRL inference? Also, have a look into the UG901 to see the example codes for SRL inference.

Thanks,

Anusheel

[chsdkj]

Anusheel,

By instantiation in my earlier post, I meant (more correctly) situations where SRLs would be inferred (from the HDL (Verilog) level), and later (in Implementation) then (presumably) be instantiated.  I understand that explicit use of SRL primitives would be a (completely) different situation.  Currently there is no RTL code extant, and so none to share.

As indicated above, the concern is regarding US/US+ devices, under the 2017.4 version of Vivado, whether there are possibly any situations where SHREG_EXTRACT may not be honored?  Specifically, for SHREG_EXTRACT = no, that SRLs might nevertheless [first be inferred and then as a result] be instantiated [inspite of the Verilog attribute having explicitly indicated not to do same]?

[chsdkj]

Anusheel,

By instantiation in my earlier post, I meant (more correctly) situations where SRLs would be inferred (from the HDL (Verilog) level), and later (in Implementation) then (presumably) be instantiated.  I understand that explicit use of SRL primitives would be a (completely) different situation.  Currently there is no RTL code extant, and so none to share.

As indicated above, the concern is regarding US/US+ devices, under the 2017.4 version of Vivado, whether there are possibly any situations where SHREG_EXTRACT may not be honored?  Specifically, for SHREG_EXTRACT = no, that SRLs might nevertheless [first be inferred and then as a result] be instantiated [inspite of the Verilog attribute having explicitly indicated not to do same]?

[anusheel]

@chsdkj

I just had a quick look into our internal database to see if any customer reported such issues recently and I did not find any SHREG_EXTRACT related issues in 2017.4. Please use the attribute in your design and let us know if you get any issues.

Thanks,

Anusheel

[chsdkj · Accepted solution]

@anusheel

Thanks.  I'll be on the lookout.