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Newbie
Newbie
416 Views
Registered: ‎06-07-2019

SPARTAN6 random behavior

Hello to every one,

I am using Xilinx ISE to synthesizes the VHDL code for a SPARTAN6. Unfortunately, it seems that part of my code is not synthesized correctly. This happens randomly without an apparent reason. For example, sometimes the SPI communication block is not implemented correctly, other time the Encoder block is not implemented and so on…. As said this happens randomly, sometimes I am just lucky and all the part of the code are implemented correctly.

I don’t know how to fix the problem I tried to change the design and goals strategies but nothing seems to work, in some cases the problem only got worse.

 

Here I have the list of all the warning that I get when I synthesize my code. I know that are so many but I would like to know if some of those warnings can generate the random behavior that I am experiencing.

I simulated my project and everithing works fine.

I just would like to smash everything with a hammer ☹

Any suggestion is more than welcome. Thank you.

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3 Replies
Highlighted
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Registered: ‎06-21-2017

Do you have complete timing constraints for your design, things like clock frequency and input/output clock to data relationships?  You also have gated clocks and are using non-dedicated clock input pins.  This can lead to timing problems.  I also suggest going through your code and the warning messages and verifying that all of the signals with
"WARNING:Xst:1710 ...has a constant value of 0..." are things that you agree are stuck at zero and not used.  The synthesizer is correct about this but you need to understand why this happened. 

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Newbie
Newbie
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Registered: ‎06-07-2019

Thank you for the answer,
I think that I have to solve at least the warning about the gate clocks. I don't know exactly how to fix it, but I will try.
Unfortunately, I can't change the pinout of the FPGA so I can't use dedicated clock input pins, however, the frequency of the input clock (SPI communication) is limited to 40 MHz. Do you think that this can be problematic?

I checked the warning 1710, the fact that the signals are set to 0 is not a problem...

thank you for your help

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Visitor
Visitor
337 Views
Registered: ‎04-08-2018

Not using dedicated clock pin is not ideal but can still work. Feed the clock signal to a clock buffer without going through any logic, then use the output of the clock buffer to drive your logics.

You also have warnings on undriven signal "WARNING:HDLCompiler:634". These often reveal coding error and needs to be clean up.

Peter Kwan, Senior FPGA Engineer
Designlinx Hardware Solution, Inc
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