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fpga_newbee99
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Registered: ‎01-25-2021

[SYNTHEIS ERROR] Auto assign bit when using Vivado 2018.1

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Hi!

I am using AHB to read/write data for verifying my IP. So far I have passed Behavior Simulation. But when I run synthesis and rerun Post-Synthesis Simulation I discovered that my HRDATA has been reduce to 8 bit not 32 bit as expected. 

When I go further into gate netlist, it turn out Vivado only take bit 10 to 3. Other bit has been set to const as shown belong.

Someone can help me? Is my RTL wrong or there is some Synthesis option of Vivado that masked my bit?

Screenshot from 2021-03-18 09-07-40.png

My block design using Kintex-7, Vivado 2018.1

Screenshot from 2021-03-18 09-04-21.png

HRDATA [31:0] reduced to \^HRDATA[10:3], other bit masked 0.

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anusheel
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Registered: ‎07-21-2014

@fpga_newbee99 

Are there any messages about optimization/trimming in the synthesis log? Please open the elaborated view and check for the connection of the trimmed bits, I think either these bits are not connected or connected to a constant inside the IP.

Thanks
Anusheel 

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anusheel
Moderator
Moderator
261 Views
Registered: ‎07-21-2014

@fpga_newbee99 

Are there any messages about optimization/trimming in the synthesis log? Please open the elaborated view and check for the connection of the trimmed bits, I think either these bits are not connected or connected to a constant inside the IP.

Thanks
Anusheel 

View solution in original post

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fpga_newbee99
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Visitor
188 Views
Registered: ‎01-25-2021

I have solve my problem. My design use both Verilog and SystemVerilog to design.

The issues when synthesis has disappeared once I convert all file to Verilog!

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