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Visitor
Visitor
5,746 Views
Registered: ‎09-10-2013

Signals renamed in synthesis netlist (NlwRenamedSig_OI_)

Hello,

 

I am trying to work on vhd netlists generated post-synthesis or post-place and route, so in order to match signal names between the netlists and my VHDL design, I added the keep attribute on all the signals, like that :

 

signal in1 : std_ulogic_vector(31 downto 0);

attribute keep : string;  
attribute keep of in1 : signal is "true"; 

 

Despite this attribute, there are some signals which are renamed in the netlists in this way :

 

NlwRenamedSig_OI_in1

 

I can't understand why some signals in the design are renamed like that while most of them conserve their original names. Does the prefix NlwRenamedSig_OI_ is the unique manner used by ISE to rename these signals ?

 

Thank you in advance for your suggestions !

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Xilinx Employee
Xilinx Employee
5,741 Views
Registered: ‎07-01-2010

Re: Signals renamed in synthesis netlist (NlwRenamedSig_OI_)

Hi,

What is the device you are targeting in this scenario?

If you are using ISE and working on 6-series/Virtex-4 /virtex-5/spartan 3 families, can you try using the -use_new_parser yes switch in other command line option in synthesis settings and see if tis helps.

Are the signals renamed are tied to some constant value1 or 0?

Regards,
Achutha
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Visitor
Visitor
5,725 Views
Registered: ‎09-10-2013

Re: Signals renamed in synthesis netlist (NlwRenamedSig_OI_)

Hi,

 

Thank you for your answer !

So the device I am using is a Spartan 6, but I tested my design on a Spartan 3 and a Virtex 5 to known if my problem could come from the device. In each case, the same signals are always renamed in the synthesis netlist.

 

I tried to put the option -use_new_parser to yes in synthesis settings but it does not resolve the naming problem for these devices.

 

The value of these signals are not always 0 or 1, it changes.

 

I have an other question about keep attribute used on signals which have custom types. For example, I have a signal which is an array of std_logic_vector but even if I put keep on it, I can't find my signal in the netlist after synthesis or place and route. I declared the signal with keep attribute like this :

 

type data_out_table is array (1 to 16) of std_ulogic_vector(7 downto 0);

signal data_out_sig : data_out_table;

attribute keep : string;

attribute keep of data_out_sig : signal is "true";

 

But then this signal has disappeared in the netlist, I think I don't use keep attribute correctly with this particular type. Is there an other manner to write it for array types ?

 

Thanks again.

 

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Xilinx Employee
Xilinx Employee
5,696 Views
Registered: ‎07-01-2010

Re: Signals renamed in synthesis netlist (NlwRenamedSig_OI_)

Hi ,

Do you mean the signal data_out_sig disappeared?
Keep attribute prevents the signal from not being absorbed into the logic block.
Try using the Save Net Flag attribute as shown in the example
VHDL Syntax
Declare the VHDL constraint as follows:
attribute S: string;
Specify the VHDL constraint as follows:
attribute S of signal_name : signal is ”{YES|NO|TRUE|FALSE }”;

For details on the Save Net Flag please check the below link :http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/cgd.pdf

Regards,
Achutha


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