02-18-2016 02:22 AM
I need your help about the scope of a static ver (a memory) inside a function.
I have two modules:
module moduleWriter(input clock, input reset, input enabled); module moduleReader(input clock, input reset, input enabled, output var[7:0] value);
Both of them uses a function which has a static variable inside:
function [7:0] memoryFunc(var opWrite, var[31:0] address, var[7:0] value = 0); static var [7:0] ram [0:1023]; if (opWrite) begin ram[address] = value; return value; end else return ram[address]; endfunction
The ram variable wants to be a buffer written from several section of code.
In the attached example I aspect to have in output leds the value 30, but I get always 0. It seems the value rams is iniziled every time I called memryFunc.
Do you have an idea about what is wrong? I am using SystemVerilog and Vivado 2015.4, simulating a VC707 board.
Attached you can find a self consistent example.
02-18-2016 03:10 AM
I think I found the possible cause:
SystemVerilog has static and automatic tasks and functions. Vivado synthesis treats all tasks and functions as automatic.
Anyone has a suggestion how can I workaround this? The other solution that comes to my mind is to pass the memory by ref, but Vivado System Verilog dialect does not support this too.
02-18-2016 06:51 AM