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Visitor
Visitor
4,463 Views
Registered: ‎01-25-2017

Strange latches in RTL analysis

Hi community, I hope that I'm not writing on wrong forum section.

I have a strange result on RTL Analysis schematic in this two cases:

 

FIRST:

signal pulse : std_logic_vector(7 downto 0);

signal s_pulse : std_logic_vector(7 downto 0);

pulse(4 downto 0) <= "00001" when s_pulse(4 downto 0)="00000" else s_pulse(4 downto 0);
pulse(7 downto 5) <= s_pulse(7 downto 5);

 

SECOND:

signal pulse2 : std_logic_vector(7 downto 0);

signal s_pulse2 : std_logic_vector(7 downto 0);

signal pulse2app : std_logic_vector(4 downto 0);
signal spulse2app : std_logic_vector(4 downto 0);

spulse2app <= s_pulse2(4 downto 0);
pulse2app <= "00001" when spulse2app="00000" else spulse2app;
pulse2 <= s_pulse2(7 downto 5) & pulse2app;

 

Result:

Rtl analysis schematic shows an RTL_LATCH on the former, but not in the latter.

 

Additional information:

Tool: Vivado 2015.4

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3 Replies
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Professor
Professor
4,434 Views
Registered: ‎08-14-2007

Re: Strange latches in RTL analysis

The problem is driving different bits of the same vector in multiple processes.  Assignments outside of a process are essentially a single statement process.  Try (in case 1)

 

process (s_pulse)

  pulse(4 downto 0) <= "00001" when s_pulse(4 downto 0)="00000" else s_pulse(4 downto 0);
  pulse(7 downto 5) <= s_pulse(7 downto 5);

end process

 

Placing these two statements in the same process should avoid multi-driven nets that could result in a latch.

 

-- Gabor
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Visitor
Visitor
4,406 Views
Registered: ‎01-25-2017

Re: Strange latches in RTL analysis

In VHDL these statements (inside a process and outside) shall be equal, maybe has Vivado a limitation analyzing these patterns? (e.g. Quartus II doesn't show the same behaviour)

 

This version:

process(s_pulse)
begin
case (s_pulse(4 downto 0)) is
   when "00000" =>
      pulse(4 downto 0) <= "00001";
   when others =>
      pulse(4 downto 0) <= s_pulse(4 downto 0);
   end case;
pulse(7 downto 5) <= s_pulse(7 downto 5);
end process;

 

works, but is a lot more verbose.

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Professor
Professor
4,381 Views
Registered: ‎08-14-2007

Re: Strange latches in RTL analysis

The issue is not "inside or outside a process" but the fact that in your original case they were in two separate "processes."  In VHDL (this is not a Vivado "feature", you'll see the same thing in ModelSim), when you make an assignment to only part of a vector in a process, the rest of that vector is also driven by the process to a default state.  This can lead to additional warnings or errors when you try to synthesize the original code (multi-driven net).  If you're trying to write the original logic less verbosely, you could do it in a single statement outside of a process like:

 

pulse <= s_pulse(7 downto 5) & "00001" when s_pulse(4 downto 0)="00000" else s_pulse;

 

Here you are clearly driving all bits of the vector in the statement, so there are no defaulted bits.

-- Gabor
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