07-11-2019 07:31 AM
Xilinx suggets that reset signal would be synchronous and high-active，but low-active reset signal should be used in my IP which is generated in AXIS protocol by HLS. I have to opposite the high-active reset signal to be as a low-active reset signal for my IP，and it makes that there are two LUTs in the netlist and finally the reset signal is high-active. However, a lot of FDCEs and FDPEs are used in my IP, which means all the registers, BRAMs and DSPs have a Asynchronous reset signal. Besides, there are to many warning about [DRC 23-20] Rule violation (REQP-1839) , [DRC 23-20] Rule violation (REQP-1839) , and so on. Is there any solutions ? Thanks !
PS : My vivado version is 2016.2 and FPGA is XC7A100T.
07-11-2019 07:41 AM
07-12-2019 12:53 AM
"bottom line, IN Xilinx FPGA's.. ( NOT ASICS )"
I corrected your quote for you.
Different FPGA families have different reset strategies based on technology.
For example, in Altera/Intel FPGAs (at least up to Stratix V, maybe 10 too) the advice is for async asserted reset, synchronously de-asserted. They have no sync reset at the flops, so sync resets are emulated with logic. Xilinx has sync resets at the flops, and a GSR that is confusing and arbitrary (and modelled horribly in simulation - the glbl.v is just a terrble fudge)
Also, Xilinx chips have always had routing problems, hence the advice to avoid resets. This isnt so bad in Altera as you can go to 90% utilisation, everything reset, without too many issues as putting an async reset on a clock net is pretty easy (and automatic).
07-12-2019 03:27 AM
Thanks for sorting out my typing.
Luckily were on the xilinx form ah, the Intel devices are as u imply , different.