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Contributor
Contributor
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Registered: ‎06-25-2017

Synchronous reset and Asynchronous reset signal

    Xilinx suggets that reset signal would be synchronous and high-active,but low-active reset signal should be used in my IP which is generated in AXIS protocol by HLS.  I have to opposite the high-active reset signal to be as a low-active reset signal for my IP,and it makes that there are two LUTs in the netlist and finally the reset signal is high-active. However, a lot of FDCEs and FDPEs are used in my IP, which means all the registers, BRAMs and DSPs have a Asynchronous reset signal. Besides, there are to many warning about [DRC 23-20] Rule violation (REQP-1839) , [DRC 23-20] Rule violation (REQP-1839) , and so on. Is there any solutions ?            Thanks !

    PS : My vivado version is 2016.2 and FPGA is XC7A100T.

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Teacher
Teacher
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Registered: ‎07-09-2009

Oh dear resets.... An old topic of much debate.

https://www.xilinx.com/support/documentation/white_papers/wp272.pdf

https://www.xilinx.com/support/documentation/white_papers/wp275.pdf


bottom line, IN FPGA's.. ( NOT ASICS )

a) only use reset if you have to, most time you will not.
b) only use synchronous reset if you have to use a reset
c) reset polarity inside the FPGA not to relevant, as its polarity can be flipped by the FPGA tools, and it does not come into effect till all registers , hence IO , have been set at configuration.

so convention, is active high in the FPGA,
its easier to rear "if rst" as opposed to "if not nRst"

IP that is used in, or came from ASICs, is active low by convention,
go figure, drive on the right or the left ???



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Scholar
Scholar
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Registered: ‎08-01-2012

@drjohnsmith 

"bottom line, IN Xilinx FPGA's.. ( NOT ASICS )"

I corrected your quote for you.

Different FPGA families have different reset strategies based on technology.

For example, in Altera/Intel FPGAs (at least up to Stratix V, maybe 10 too) the advice is for async asserted reset, synchronously de-asserted. They have no sync reset at the flops, so sync resets are emulated with logic. Xilinx has sync resets at the flops, and a GSR that is confusing and arbitrary (and modelled horribly in simulation - the glbl.v is just a terrble fudge)

Also, Xilinx chips have always had routing problems, hence the advice to avoid resets. This isnt so bad in Altera as you can go to 90% utilisation, everything reset, without too many issues as putting an async reset on a clock net is pretty easy (and automatic). 

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Teacher
Teacher
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Registered: ‎07-09-2009

Thanks for sorting out my typing.

 

Luckily were on the xilinx form ah, the Intel devices are as u imply , different. 

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