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Visitor
Visitor
660 Views
Registered: ‎08-24-2020

[Synth 8-196] conditional expression could not be resolved to a constant

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Above is my program,the following error code appears when I synthesize.

[Synth 8-196] conditional expression could not be resolved to a constant 

I use Vivado 2018.3.

 

 

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Xilinx Employee
Xilinx Employee
579 Views
Registered: ‎07-21-2014

Hi @lactiv7 

 

Can you please attach rtl file here instead of code snippet. It would help to understand issue more clearly.

 

-Shreyas

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Visitor
Visitor
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Registered: ‎08-24-2020

Hi  @aher  this is my rtl code.

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Xilinx Employee
Xilinx Employee
540 Views
Registered: ‎07-21-2014

Hi @lactiv7 

 

The project you have attached only has top.v RTL file. Please also add RTL file to reproduce the issue you have mentioned.

 

Regards,

Shreyas

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Scholar
Scholar
508 Views
Registered: ‎09-16-2009

Yes, please use the "insert" code tag button on the forums and paste text files showing a small example.  It's much easier for us to help you that way.

But the short answer, you need to use the "+:", and "-:" range/width selectors in verilog, instead of the variable MSB:LSB that you're doing.

There's been much written about the above - but it's a difficult search term/expression. Dig around some, and let us know if your stilling having trouble.  Folks can dig up more pointers for you if neccesary.

Regards,

Mark

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Visitor
Visitor
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Registered: ‎08-24-2020

sorry,this is my complete rtl code

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