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valten
Visitor
Visitor
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Registered: ‎05-24-2017

[Synth 8-2490] overwriting previous definition of module

Hello,

 

I am currently trying to implement a design on an Artix-7 fpga for my company. This design includes several IPs, these IPs including RTL modules (in Verilog) bearing the same name, but with a different definition (not the same number of ports etc ...).

I cannot change the name of the modules, because these are "shelf" IPs that i cannot modify. I tried assigning them to different libraries, so that all the IP1 files are compiled in the "IP1_lib" and same for IP2. I checked the xml file and all the files are attributed to the right library.

I can't seem to find a solution to my problem by looking at other related topics. AR#58282 only tells me to compile these files in different libraries, which i did. The problem could be that these libraries were not created the right way, but i do not find that much topics related to library creation in Vivado either.

I am using Vivado 2015.4 (company licence).

 

I thank you in advance for all the help you could bring to me in order to resolve this issue.

 

Valentin

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jmcclusk
Mentor
Mentor
2,926 Views
Registered: ‎02-24-2014

According to UG901, libraries in Verilog (or SystemVerilog) are not yet supported in Vivado 2018.1.     I think your only choice is to find a way to modify the names of the modules so that they are unique.    Creating Verilog IP libraries with identical module names seems like a pretty bad idea.     You might be able to get the design to link a netlist if you create DCP files with a unique wrapper name, but this might fail too, because of the ambiguity of the module names.    

 

Bottom line,  different IP blocks need different names.

Don't forget to close a thread when possible by accepting a post as a solution.
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