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dmitry1417
Explorer
Explorer
6,492 Views
Registered: ‎02-24-2016

[Synth 8-2611] redeclaration of ansi port state is not allowed -> how to avoid?

Hi All,

 

I'm receiving the following warning during the synthesis:


 

[Synth 8-2611] redeclaration of ansi port state is not allowed ["C:/DmitryL/PROJECTS/BioSense/ACL_TX/RTL/dds_fsm/dds_fsm.params.v":24]


 

Here is the code:

//** MEM IF FSM States
enum {IDLE, //
      CH0,  //
      CH1,  //
      CH2   //
      } state, nxt_state;

As you can see, this is just the FSM states declaration. So, what's wrong? What does the warning mean? How to avoid it?

 

Thank you!


 

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2 Replies
syedz
Moderator
Moderator
6,485 Views
Registered: ‎01-16-2013

@dmitry1417,

 

Can you please share the complete RTL code?

 

The warning states that the port is getting re declared. 

For Example in ISE:

module top(
    input clk,
    ......

    output [71:0] out
    );

    ......

    reg [71:0] out;

 

 

Will give the warning on reg [71:0] out. XST will give warning, when it comes across the port direction inside the port list and then when it comes across the data type of that port outside the port list.

The warning message can be removed by merging the data type declaration with the port direction declaration. Here is the example verilog code that reflects this change:

 

module top(
    input clk,
    ......

    output  reg  [71:0] out
    );

 

--Syed

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anusheel
Moderator
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6,433 Views
Registered: ‎07-21-2014

@dmitry1417

 

Can you show us the complete code to understand the issue? Also, check if you are importing any module or package in your SystemVerilog file which may result in redeclaration. 

 

Thanks,
Anusheel
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