02-27-2020 01:31 AM
Vivado2019.2 giving [Synth 8-295] found timing loop critical warning durring syathesis run. any idea, why i am facing this issue in vivado 2019.2. is it tool issue ?
02-27-2020 01:40 AM
Open synthesized design and run check_timing report by running the following command. This report will show you the loop on which tool is complaining. You need to fix it.
check_timing -verbose -name timing_1
02-27-2020 03:12 AM
02-27-2020 03:47 AM
Its a design issue. You should get the loop from the report showing the output of combinational logic getting connected back to input logic.
02-27-2020 04:41 AM
One type of timing loop is described on page 309 of UG906(v2019.1) as follows:
Combinatorial timing loops are created when the output of combinatorial logic is fed back to its input, resulting in a timing loop. This loop unnecessarily increases the number of cycles by infinitely going around the same path and cannot be timed. To resolve the timing loop, the Vivado IDE disables the timing arc on the cell in the loop.
02-27-2020 11:50 PM
03-01-2020 09:21 PM
07-07-2020 01:09 PM
07-07-2020 04:58 PM
-see the following post for instructions on locating the timing loop:
07-10-2020 11:12 AM - edited 07-10-2020 11:13 AM
Are you using any kind of Custom Attributes on the signal in RTL?
To check this as @syedz mentioned Open Synthesized Design -> do a Check Timing -> Select the net / cell for this loop -> Right Click -> Go to Source.
Previously there were issues reported in which the attributes like syn_preserve and async_reg were not properly handled by synthesis and tool inferred timing loops on those signals.
Can you check if this is the case?
Also, can you try this in the latest release of vivado i.e. 2020.1?
07-14-2020 10:45 PM
--> Open synthesized design
--> type "check_timing -verbose -name timing_1" in the tc console
this will report the paths were combo loops are present.
The example below will give you an idea to overcome this issue,
if(a = '1')then
if(sop = '1')then
In the above example, we are using signal 'a' to generate signal 'a' back again this is called a combo loop.
you need to convert it to a sequential block.
11-20-2020 06:44 PM - edited 11-20-2020 07:15 PM
drjohnsmith: Although I am not the OP here, I had a situation where I had a half-dozen timing (combinatorial) loops out of an historical design for an IBM 1410 done to the IBM logic block level. It simulated just fine, because in the "real world" other signals were such that the conditions necessary for the timing loop never actually occurred because of those other signals. So that is one reason why it might not be caught during simulation. Even at that, only two of those were blocking generating a bitstream.
In my case it took me a few hours to track it down because 1) It was not an issue I had run into before during the pilot where I recreated a design I was involved in as a student in 1972 and 2) The tool was optimizing away some of the intermediate logic elements. Turning down the level of optimization (I set flatten_hierarchy none) along with "Go To Source" available on *some* of the logic elements helped me to be able to track it down, because then I could see signal names to follow the loop.
(Interestingly, in Vivado 2018.2, without flatten_hierarchy set to none, Go To source on the LUT in the schematic sent me off to something that was not even closely related to the issue, perhaps because the LUT was being used in more than one place.)