cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
olivierporchy
Contributor
Contributor
789 Views
Registered: ‎06-18-2019

[Synth 8-5826] no such design unit <file> in library 'work'

Jump to solution

Dear all

On a basic project with mixed vhdl and verilog files, when I launch 'synthesis' Vivado returns the error showed in the attached "capture0" file.

But a "report_compile_order" tcl command shows that the file is in the right library (see attached "capture" file).

Anybody to help me please ?

Olivier

 

Capture0.PNG
Capture.PNG
0 Kudos
1 Solution

Accepted Solutions
olivierporchy
Contributor
Contributor
773 Views
Registered: ‎06-18-2019

Thanks for answer.

Names match between verilog and vhdl.

It now works well. What I did is to declare the component in a vhdl wrapper that calls the verilog file...

 

View solution in original post

0 Kudos
2 Replies
TomH_BAH
Observer
Observer
781 Views
Registered: ‎06-30-2020

My understanding of mixed language use is that VHDL instantiating Verilog is case sensitive. Double check the VHDL instantiation against the Verilog module name to make sure they match. If the file name is an indicator, the module is in all uppercase, where the error shows the instance is lowercase.

0 Kudos
olivierporchy
Contributor
Contributor
774 Views
Registered: ‎06-18-2019

Thanks for answer.

Names match between verilog and vhdl.

It now works well. What I did is to declare the component in a vhdl wrapper that calls the verilog file...

 

View solution in original post

0 Kudos