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Adventurer
Adventurer
1,568 Views
Registered: ‎02-08-2016

Synthesis Bug. Vivado Synthesis Tool fails during gated clock latch conversion. Vivado 2017.2

Hi this applies to Vivado 2017.2

 

Synthesis crashes during clock gating latch conversion.

 

As an ASIC to FPGA engineer I have suffered many hours of wasted time due to problems with synthesis tool not dealing well with gated clock latches.

 

Today I discovered that if use a gated clock latch, clocked by a clock CLK,

AND have an output from the design which is driven by the gated clock latch, then the synthesis tool will crash.

 

Below are the sources : see the comment "THIS WILL CRASH TOOL"

Also included are a bunch of screen shots,

 

To make the synthesis tool fail and abort , you need to set the Gated Clock Conversion mode to "auto"

To make the synthesis tool complete , but fail to convert gated clock latch , switch Gated Clock Conversion mode to "on"

 

To see error report when synth fails see Synthfails.png

 

More info. Please ask me.

 

Cheers Simon

 

################################ Verilog  Source code #######################################


module stdcell_clk_gate (
input wire clk_i,
input wire en_i,
input wire test_en_i,

output wire clk_o
);


reg latched_en;
always @(clk_i or test_en_i or en_i) begin
if (!clk_i)
latched_en <= test_en_i || en_i;
end


assign clk_o = latched_en & clk_i;


endmodule // stdcell_clk_gate

 

`timescale 1ns / 1ps


module top(
input clk,
input datain,
input cntrl,
input reset,
output dataout,
output clkout
);

wire clk_out , clk_buf ;
BUFG bufg1 ( .I(clk), .O(clk_buf));

stdcell_clk_gate u_gated_clock_latch(
.clk_i(clk_buf),
.en_i(cntrl),
.test_en_i(1'b0),
.clk_o(clk_out) );


// Uncomment next line THIS WILL CRASH TOOL DURING SYNTHESIS IN AUTO mode
assign clkout = clk_out ;

reg data_reg ;

always @(posedge clk_out or posedge reset) begin
if (reset)
data_reg <= 1'b0 ;
else
data_reg <= datain ;
end

assign dataout = data_reg ;

endmodule

 

 

 

 

GOODSYNTH.png
GoodELAB.png
badelab.png
Synthfails.png
SYNTHNOCONVERT.png
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5 Replies
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Moderator
Moderator
1,543 Views
Registered: ‎02-07-2008

@simonh_bwt, using the code you put in the initial post, I created the attached 2017.2 project, but did not encounter any crash. Can review the attached project to see if you can make it crash? I tried it with line 47 commented and uncommented with synthesis successfully finishing on both occasions.

 

If you can, can you then attached the project so I can run some further tests?

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Highlighted
Adventurer
Adventurer
1,536 Views
Registered: ‎02-08-2016

Hi did you set the synthesis property -gated_clock_conversion to auto ?
Also did you create a clock :
create_clock -name clock -period 100.0 [get_ports clk]
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Xilinx Employee
Xilinx Employee
1,534 Views
Registered: ‎02-16-2014

Hi @simonh_bwt

 

I am able to reproduce this issue. Checking this further and will update you.

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Highlighted
Adventurer
Adventurer
1,532 Views
Registered: ‎02-08-2016

Hi Pulim I have tarred up the complete project.

 

Please find it attached

 

Let me know if anything is missing !

 

Cheers

Simon

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Highlighted
Xilinx Employee
Xilinx Employee
1,525 Views
Registered: ‎02-16-2014

Hi @simonh_bwt

 

I am able to reproduce this crash with vivado next release internal build and filed a CR#992781 to fix this issue.

Regarding the vivado fail to convert gated clock latch with clock_gating  "on" option, I am checking further and will update you.