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nkraemer
Contributor
Contributor
672 Views
Registered: ‎03-05-2019

Synthesis Crashes with EXCEPTION_ACCESS_VIOLATION when Parameters are Forgotten

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I'm working with Vivado 2019.2 on Windows 10. I recently tried to instantiate a SystemVerilog module that looks like the following:

module my_module#(
      parameter W_A,
      parameter W_B,
      parameter C
   ) (
   input logic            clk,
   input logic            rst,
   input logic [W_B-1:0]  scale1[C-1:0],
   input logic [W_B-1:0]  scale2[C-1:0],
   custom_interface.recv  samples_in,
   custom_interface.drv   samples_adj
);

 I initially forgot the parameters when instantiating the module, so instantiation looked like the following:

my_module my_module_inst (
   .clk (clk),
   .rst (ctrl.rst),
   .scale1 (ctrl.scale1),
   .scale2 (ctrl.scale2),
   .samples_in (samples_in),
   .samples_out (samples_out)
);

When I do this and try to run synthesis, Synthesis fails, but there are no error messages in the messages tab. The log tab/synthesis shows the following:

Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 5684 
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 909.605 ; gain = 234.332
---------------------------------------------------------------------------------
Abnormal program termination (EXCEPTION_ACCESS_VIOLATION)
Please check 'C:/path/to/project/synth_1/hs_err_pid4940.log' for details

When I properly included the parameters, synthesis ran successfully, but I spent quite a while trying to figure out what was wrong.

Is this a known bug and fixed in future versions of Vivado? I've attached the log file and I can send the .dmp file to Xilinx if that would be useful.

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Accepted Solutions
aher
Xilinx Employee
Xilinx Employee
470 Views
Registered: ‎07-21-2014

Hi @nkraemer,

 

I have got the project, and I could reproduce the issue in latest vivado version as well.

Looks like the issue comes up when submodule has interface ports and parameters are not passed from the top. Also parameters in submodule are not initialized and port width has dependency on it.

I have filed CR for this issue so that tool will error out in this case in the future version.

 

Regards,

Shreyas

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aher
Xilinx Employee
Xilinx Employee
629 Views
Registered: ‎07-21-2014

Hi @nkraemer

Although issues were reported previously on parameters usage, I believe, Only passing or missing parameters during instantiation would not cause the elaboration crash. After passing parameters, is logic inside submoudle getting effected? I guess from the rtl that you are also using interfaces. Can you attach dump file to retrieve some information?

Also is it possible for you to share testcase to debug issue locally? if yes I can send you ezmove link for secured transfer.

 

-Shreyas

----------------------------------------------------------------------------------------------
Try to search answer for your issue in forums or xilinx user guides before you post a new thread.

Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query.
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----------------------------------------------------------------------------------------------
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nkraemer
Contributor
Contributor
591 Views
Registered: ‎03-05-2019

Thank you for the quick response Shreyas. I have a sample project I can share with you. Please DM me with the details for the ezmove.

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aher
Xilinx Employee
Xilinx Employee
471 Views
Registered: ‎07-21-2014

Hi @nkraemer,

 

I have got the project, and I could reproduce the issue in latest vivado version as well.

Looks like the issue comes up when submodule has interface ports and parameters are not passed from the top. Also parameters in submodule are not initialized and port width has dependency on it.

I have filed CR for this issue so that tool will error out in this case in the future version.

 

Regards,

Shreyas

----------------------------------------------------------------------------------------------
Try to search answer for your issue in forums or xilinx user guides before you post a new thread.

Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query.
Give Kudos (star provided in right) to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post

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