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barb.reveles
Visitor
Visitor
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Registered: ‎01-23-2020

Synthesis Error: DRc 23-20 Rule Violation MDRV-1

So i keep getting this error about Multiple Driver Nets and i can't seem to locate the problem anywhere in my code. Can someone help me?

[DRC 23-20] Rule violation (MDRV-1) Multiple Driver Nets - Net h7/m8/Count/q_reg[16]_0 has multiple drivers: h7/m8/Count/q_reg[0]/Q, h7/m8/Count/q_reg[16]/Q

Here is all the modules that it mentions:

H7: Hex to SSD Decoder

module hex_ssd(clk, rst, Cathode,btn);
input clk, rst, btn;
output [7:0] Cathode;
reg [7:0] Cathode;
wire [3:0] HexVal;
mux m8 (.clk(clk),.rst(rst),.out(HexVal),.inVal(inVal),.val(btn));
always@(*)
    case(HexVal)
        4'h0: Cathode = 8'hc0;
        4'h1: Cathode = 8'hf9;
        4'h2: Cathode = 8'ha4;
        4'h3: Cathode = 8'hb0;
        4'h4: Cathode = 8'h99;
        4'h5: Cathode = 8'h92;
        4'h6: Cathode = 8'h82;
        4'h7: Cathode = 8'hf8;
        4'h8: Cathode = 8'h80;
        4'h9: Cathode = 8'h98;
        4'ha: Cathode = 8'h88;
        4'hb: Cathode = 8'h83;
        4'hc: Cathode = 8'hc6;
        4'hd: Cathode = 8'ha1;
        4'he: Cathode = 8'h86;
        4'hf: Cathode = 8'h8e;
        endcase
endmodule
 
m8: multiplexer
 
module mux( clk, rst, out, inVal,val);
input clk, rst,val;
input [15:0] inVal;
output [3:0] out;
reg [3:0] out;
wire [2:0] cathode;
wire [31:0] In;
assign In = {inVal[15:0],inVal[15:0]};
cathode cath(.clk(clk),.rst(rst),.cathode(cathode));
count32 Count(.clk(clk),.rst(rst),.count(val),.q(In));
always@(*)
    begin
        case(cathode)
            3'b000 : out = In[3:0];
            3'b001 : out = In[7:4];
            3'b010 : out = In[11:8];
            3'b011 : out = In[15:12];
            3'b100 : out = In[19:16];
            3'b101 : out = In[23:20];
            3'b110 : out = In[27:24];
            3'b111 : out = In[31:28];
        endcase
    end
   
endmodule
 
Count: 32-bit counter
module count32(clk, rst, count, q);
input clk, rst, count;
output [31:0] q;
reg [31:0] q;
wire inc;

button but(.clk(clk),.rst(rst),.button(count),.db(inc));
always@(posedge clk, posedge rst)
    if (rst) q <= 32'b0; else
    if (inc) q <= q + 32'b1;
   
endmodule
 
 
the 'q' is what the error is about but i don't see anything wrong with the always loop.
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5 Replies
rshekhaw
Xilinx Employee
Xilinx Employee
974 Views
Registered: ‎05-22-2018

Hi @barb.reveles ,

This message is informing you that there is a signal  that is being assigned / updated / driven in two different always blocks.

An example of a piece of code that would generate such an error is shown below:

always @ (posedge CLK)
y = y + 1;

 

always @ (posedge CLK2)
y = y + 3;

Solution:


It may be easier to use the elaborated netlist (RTL Analysis → Open Elaborated Design) to identify the signal by finding the signal in error using ctrl+F on open elaborated design.

Thanks,

Raj.

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miker
Xilinx Employee
Xilinx Employee
938 Views
Registered: ‎11-30-2007

I think your issue is that you are driving the 'In[31:0]' signal in "m8" by both the 'q' output of the "count32" module and in your top-level port 'inVal'.

m8: multiplexer

module mux( clk, rst, out, inVal,val);
input clk, rst,val;
input [15:0] inVal;
output [3:0] out;
reg [3:0] out;
wire [2:0] cathode;
wire [31:0] In;
assign In = {inVal[15:0],inVal[15:0]}; -- Driving 'In' from both count32 instantiation 'q' output and with 'inVal' top-level port
cathode cath(.clk(clk),.rst(rst),.cathode(cathode));
count32 Count(.clk(clk),.rst(rst),.count(val),.q(In));
always@(*)
    begin
        case(cathode)
            3'b000 : out = In[3:0];
            3'b001 : out = In[7:4];
            3'b010 : out = In[11:8];
            3'b011 : out = In[15:12];
            3'b100 : out = In[19:16];
            3'b101 : out = In[23:20];
            3'b110 : out = In[27:24];
            3'b111 : out = In[31:28];
        endcase
    end
   
endmodule

 

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anusheel
Moderator
Moderator
891 Views
Registered: ‎07-21-2014

@barb.reveles 

As already mentioned in the above post, there are two drivers for In. Please use the elaborated design to see the connection of In.

Thanks
Anusheel 

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barb.reveles
Visitor
Visitor
825 Views
Registered: ‎01-23-2020

“In” is supposed to come from the 32-bit counter which is why it’s driving into q, but the value “InVal” are the switches on the fpga, so how can I implement this without getting the error ?

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barb.reveles
Visitor
Visitor
803 Views
Registered: ‎01-23-2020

debounce snip.PNG

 

here is the elaborated design. "InVal" are the switches on the Nexys A7 board. However, i'm having trouble connecting the correct value to it. Each switch represents one of the 16 digits in the seven segment display. I tried connecting it to HexVal in my decoder but it also didn't work, could you help me?  

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