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forsterjan
Visitor
Visitor
14,308 Views
Registered: ‎12-05-2012

Synthesis Error: INTERNAL_ERROR:Xst:cmain.c:3423:1.29 - Process will terminate

Hi,

 

I started synthesizing my design for a Virtex 5 LX330 in ISE 14.3 & 14.4 and after a few minutes I got the following strange error without any further description:

 

INTERNAL_ERROR:Xst:cmain.c:3423:1.29 - Process will terminate

 

Any ideas what leads to this error?

 

Jan

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15 Replies
debrajr
Moderator
Moderator
14,305 Views
Registered: ‎04-17-2011

As you are using V-5, try using -use_new_parser yes switch in XST Command Line Option. Read http://www.xilinx.com/support/answers/40377.htm for more info.
Regards,
Debraj
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forsterjan
Visitor
Visitor
14,297 Views
Registered: ‎12-05-2012

Hi,

 

I already tried the -use_new_parser switch in the command line options. The error is always at the same point, the advanced hdl synthesis, but it occurs independantly of a special file.

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forsterjan
Visitor
Visitor
14,272 Views
Registered: ‎12-05-2012

Hi together,

 

I solved the problem setting the "-keep_hierarchy" parameter to soft.

Hope I could help somebody with this information.

 

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sharonzhang
Newbie
Newbie
14,035 Views
Registered: ‎04-20-2013

thank you very much. i met the same problem. now it is solved as your guide.

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evgenis1
Advisor
Advisor
13,347 Views
Registered: ‎12-03-2007

Hi,

 

I've got the same xst error while compiling my Zynq 7045 design with PlanAhead. The design is based on PCIe TRD for zc706 board. XST "broke" after I made a few minor changes in the XPS system.

 

Unfortunately, setting "-keep_hierarchy soft" didn't fix the issue. And of course, I validated that the setting took effect in the SRP file.

 

Thanks,

Evgeni

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achutha
Xilinx Employee
Xilinx Employee
13,309 Views
Registered: ‎07-01-2010

Hi Evgeni,

Do you still see the issue?
Can you please share the srp report file?

Thanks,
Ram
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evgenis1
Advisor
Advisor
13,295 Views
Registered: ‎12-03-2007

I certainly do see the issue.

 

Attached is the report. I removed all paths and module names from it.

 

 

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achutha
Xilinx Employee
Xilinx Employee
13,290 Views
Registered: ‎07-01-2010

Thanks for providing the report.

 

I see that the internal error is caused during the optimization of "trace_control_interface" module , is this IP in the EDK system or an separate module .

 

Is it possible to comment(not to use in the project,synthesis translate on/off can also be used) the "trace_control_interface" module and run the synthesis and see if you still see the issue. 

 

The above test will let us know if "trace_control_interface" module is the root cause of this issue.

 

regards,

Ram

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evgenis1
Advisor
Advisor
13,287 Views
Registered: ‎12-03-2007

Hi Ram,

 

Thanks for taking a look at this issue.

 

Actually, I opened a case with Xilinx Tech Support on this issue. They have the entire project, and hopefully this issue will be resolved soon.

 

 

Thanks,

Evgeni

 

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sathho99
Newbie
Newbie
7,329 Views
Registered: ‎09-19-2013

I use ISE 14.6 and "-keep_hierarchy" = soft. did not work for me.
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viviany
Xilinx Employee
Xilinx Employee
7,313 Views
Registered: ‎05-14-2008

If no easy solution (-use_new_parser yes or any other synthesis options) for this, you have to refer to AR40377 and follow the debugging steps in it.

http://www.xilinx.com/support/answers/40377.htm

 

Thanks

Vivian

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achutha
Xilinx Employee
Xilinx Employee
7,260 Views
Registered: ‎07-01-2010

Hi,

 

Are you still seeing the Internal Error ?

 

Regards,

Achutha

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khs8391
Visitor
Visitor
3,769 Views
Registered: ‎02-16-2015

I always try all things.. But, it is happend always 

"Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.  "

 

anybody help me please... I am very hard time..

 

I add .syr file

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syedz
Moderator
Moderator
3,767 Views
Registered: ‎01-16-2013

@khs8391,


Please share the ISE archive project to debug the issue and provide you the solution for same.

 Since you are using Zynq device, Is it possible to run synthesis in Vivado?

 

From the shared synthesis log file, check if the below similar forums threads are helpful:

https://forums.xilinx.com/t5/Synthesis/Synthesize-stops-with-aborting-GetDataRange/td-p/221715

 

https://forums.xilinx.com/t5/Synthesis/XST-fails-synthesis-without-errors-for-some-types-of-FPGAs/td-p/546941

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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anusheel
Moderator
Moderator
3,737 Views
Registered: ‎07-21-2014

@khs8391

 

As you are using 7series device, you need not to use -use_new_parser switch, tool will automatically pick it.

Also, are you using any multi-dimensional arrays in your design? Can you try to narrow down to one RTL file?

 

Thanks,
Anusheel
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