cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Jack9117
Visitor
Visitor
730 Views
Registered: ‎02-14-2021

Synthesis Fails without error code

Hello everyone,

Over the last week, an issue has developed for a particular project during synthesis after i changed the width of two wires. The synthesis runs for around 20 minutes and then fails without an error code. I've attached the runme.log file and it shows during the "RTL Optimization Phase 2" it uses more memory (if it is actually referring to RAM) than my computer has. I'm relatively new to Vivado and Verilog in general so I'm not really sure what the issue is.

Any information would be great.

 

Thanks in Advance,

Jack

0 Kudos
10 Replies
drjohnsmith
Teacher
Teacher
716 Views
Registered: ‎07-09-2009

well done for posting the log file

any of these of use 

https://www.xilinx.com/support/answers/66106.html

https://forums.xilinx.com/t5/Synthesis/Synthesis-failed-without-any-messege/td-p/1019891

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Jack9117
Visitor
Visitor
704 Views
Registered: ‎02-14-2021

I'm not sure, as I'm able to synthesise other projects and (i think) the first link is about universal issues so I'm not sure if it applies.

As for the second link, I'll see if i can work out how to run the synthesis from command line and if it yields any results.

 

Thanks,

Jack

watari
Professor
Professor
654 Views
Registered: ‎06-16-2013

Hi @Jack9117 

 

It's requirement memory issue during synthesis and/or implement.

What is your target FPGA device ?

 

Xilinx prepares memory requirement as the following URL.

Would you refer it ?

 

https://www.xilinx.com/products/design-tools/vivado/memory.html

 

Best regards,

0 Kudos
Jack9117
Visitor
Visitor
586 Views
Registered: ‎02-14-2021

The target board is a Kintex-7 xc7k160tffg676-3, so from the link it should only be using 3GB at most. especially odd since in the runme file it gets to "Memory (MB): peak = 37427.547" during the RTL optimisation.Is it maybe that the board isn't able to manage the size of the project (though this seems unlikely)?

Thanks,

Jack

0 Kudos
drjohnsmith
Teacher
Teacher
580 Views
Registered: ‎07-09-2009

What's the OS on your PC. 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Jack9117
Visitor
Visitor
579 Views
Registered: ‎02-14-2021

Windows 10 Education. I'm not sure what the difference between the student edition and home premium are specifically.

0 Kudos
drjohnsmith
Teacher
Teacher
556 Views
Registered: ‎07-09-2009

Well thats not a supported OS,

but looking here, 

   https://en.wikipedia.org/wiki/Windows_10_editions#Comparison_chart

 

I can't see any obvious reason it would not run.

Are you on a 64 bit system ?

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Jack9117
Visitor
Visitor
551 Views
Registered: ‎02-14-2021

Yeah its 64-bit.

Thanks,

Jack

0 Kudos
watari
Professor
Professor
505 Views
Registered: ‎06-16-2013

Hi @Jack9117 

 

Routing procedure (a part of implementation) consume memory if your design has many clock tree and/or critical timing path and/or congestion issue.

So I guess you are facing this issue.

 

Here is solution for this issue (on linux). But I'm not sure it's for Windows 10 Student.

But would you try it ?

 

Change swap size to twice of real memory size.

 

Best regards,

0 Kudos
Jack9117
Visitor
Visitor
438 Views
Registered: ‎02-14-2021

Hi @watari ,

I'm a bit unsure of what you mean as the error isn't during the implementation stage, unless I am just misunderstanding you?

 

Thanks,

Jack

0 Kudos