02-15-2021 06:46 AM
Over the last week, an issue has developed for a particular project during synthesis after i changed the width of two wires. The synthesis runs for around 20 minutes and then fails without an error code. I've attached the runme.log file and it shows during the "RTL Optimization Phase 2" it uses more memory (if it is actually referring to RAM) than my computer has. I'm relatively new to Vivado and Verilog in general so I'm not really sure what the issue is.
Any information would be great.
Thanks in Advance,
02-15-2021 08:07 AM
well done for posting the log file
any of these of use
02-15-2021 08:38 AM
I'm not sure, as I'm able to synthesise other projects and (i think) the first link is about universal issues so I'm not sure if it applies.
As for the second link, I'll see if i can work out how to run the synthesis from command line and if it yields any results.
02-15-2021 01:41 PM
It's requirement memory issue during synthesis and/or implement.
What is your target FPGA device ?
Xilinx prepares memory requirement as the following URL.
Would you refer it ?
02-16-2021 02:31 AM
The target board is a Kintex-7 xc7k160tffg676-3, so from the link it should only be using 3GB at most. especially odd since in the runme file it gets to "Memory (MB): peak = 37427.547" during the RTL optimisation.Is it maybe that the board isn't able to manage the size of the project (though this seems unlikely)?
02-16-2021 05:12 AM
Well thats not a supported OS,
but looking here,
I can't see any obvious reason it would not run.
Are you on a 64 bit system ?
02-16-2021 01:29 PM
Routing procedure (a part of implementation) consume memory if your design has many clock tree and/or critical timing path and/or congestion issue.
So I guess you are facing this issue.
Here is solution for this issue (on linux). But I'm not sure it's for Windows 10 Student.
But would you try it ?
Change swap size to twice of real memory size.