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Observer
Observer
4,581 Views
Registered: ‎11-07-2013

Synthesis Report not Updating after Successive Runs

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Hi,

 

I'm using ISE 14.4 and it has been working fine, but now when I run synthesis on my design, the report in the design summary doesn't update.  It keeps an old report and time generated in the "Design Summary".  In the console window, I see the correct report.  The problem is that when I try to map, it uses the top component that was used in the old report, which has too many outputs so it reports that too many IOBs are used for the device and the old report shows the wrong top module name.  

 

I've tried to close and reopen ISE, but that didn't work so I restarted my PC and rerun synthesis to no avail.  I didn't do anything out of the ordinary to trigger this, just rerun synthesis. Anyone have any tips or suggestions?  Thank you.

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Observer
Observer
5,756 Views
Registered: ‎11-07-2013

Looks like the problem has fixed itself after repeatedly switching top modules and synthesizing my design.  I'll accept this as the solution.

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Observer
Observer
4,579 Views
Registered: ‎11-07-2013

UPDATE: When I reselect the component that shows up in the old report as the top module again, the design summary updates, but when I select my actual top component, the synthesis report in the Design Summary window reverts back to the old date and time.  Hope this provides some more insight. 

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Highlighted
Observer
Observer
5,757 Views
Registered: ‎11-07-2013

Looks like the problem has fixed itself after repeatedly switching top modules and synthesizing my design.  I'll accept this as the solution.

View solution in original post

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