11-14-2018 05:29 AM
There is a bug where if you map an aggregate in a port map using an unconstrained array (or record type) it maps the arrays by index, rather than taking into account the direction of the array against VHDL rules.
In the following code, IP0 should ultimately connect to OP0, and IP1 -> OP1
But alas no, IP0 -> OP1 and IP1 -> OP0
package pkg is
type slv_array_t is array(natural range <>) of std_logic_vector;
end package pkg;
entity ent is
N : natural := 2
ip : in slv_array_t(N-1 downto 0); -- stll unconstrained
op0 : out std_logic_vector;
op1 : out std_logic_vector
end entity ent;
architecture rtl of ent is
op0 <= ip(0);
op1 <= ip(1);
end architecture rtl;
entity top is
ip0 : in std_logic_vector(7 downto 0);
ip1 : in std_logic_vector(7 downto 0);
op0 : out std_logic_vector(7 downto 0);
op1 : out std_logic_vector(7 downto 0)
end entity top;
architecture rtl of top is
inst : entity work.ent
generic map (
N => 2
port map (
ip => (ip1 & ip0),
op0 => op0,
op1 => op1
end architecture rtl;
And here is the elaborated design:
Let me explain what is going on:
ent has an input port decalred (N-1 downto 0).
In the port mapping, I create an aggregate (ip1 & ip0).
In VHDL, this defaults (0 to 1), but the port its mapping to is (1 downto 0). So mapping should be 0 -> 1 and 1 ->0 as per VHDL rules.
Unfortunately Vivado seems to think It can connect 0 -> 0 and 1 -> 1. This is NOT how VHDL mapping works, hence an elaboration bug.
11-14-2018 08:05 PM
I am looking into your source code. I will get back to you with the outcomes.
11-15-2018 01:22 AM - edited 11-15-2018 01:26 AM
If I change the code to be more 1993 style (code still set as VHDL 2008), it works as expected. Only change is:
type slv_array_t is array(natural range <>) of std_logic_vector(7 downto 0);
So I assume this is a difference in the way Vivado is handling 2008 unconstrained arrays (and records, because in my real code I have an array of records as a port - and it also exhibits the same issue as #1)
11-23-2018 03:47 AM
I used the code posted in your first reply and ran it in 2018.2 and I don't see any issue. Please let me know which version of Vivado you are using or if I missed anything.
11-23-2018 04:24 AM - edited 11-23-2018 05:32 AM
11-25-2018 12:31 AM
This is Vivado 2018.2
As you have shown, you are seing the same problem as me (please look at the paths all the way through the diagram). If you modify the type in the package (no other code mods), as per #3, the problem goes away (as I show in the picture inn #3, IP0 -> OP0, and IP1 -> OP1). This appears to be a bug in the way Vivado interprets VHDL2008 aggregates when done in a port map.
01-08-2019 02:18 AM
01-09-2019 10:52 PM