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Scholar richardhead
Scholar
697 Views
Registered: ‎08-01-2012

Synthesis doesnt know difference between downto and to

There is a bug where if you map an aggregate in a port map using an unconstrained array (or record type) it maps the arrays by index, rather than taking into account the direction of the array against VHDL rules.

In the following code, IP0 should ultimately connect to OP0, and IP1 -> OP1

But alas no, IP0 -> OP1 and IP1 -> OP0

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package pkg is
type slv_array_t is array(natural range <>) of std_logic_vector;
end package pkg;


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.pkg.all;

entity ent is
generic (
N : natural := 2
);
port (
ip : in slv_array_t(N-1 downto 0); -- stll unconstrained
op0 : out std_logic_vector;
op1 : out std_logic_vector
);
end entity ent;

architecture rtl of ent is
begin
op0 <= ip(0);
op1 <= ip(1);
end architecture rtl;



library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.pkg.all;

entity top is
port (
ip0 : in std_logic_vector(7 downto 0);
ip1 : in std_logic_vector(7 downto 0);

op0 : out std_logic_vector(7 downto 0);
op1 : out std_logic_vector(7 downto 0)
);
end entity top;

architecture rtl of top is
begin

inst : entity work.ent
generic map (
N => 2
)
port map (
ip => (ip1 & ip0),
op0 => op0,
op1 => op1
);

end architecture rtl;

And here is the elaborated design:


switch.png

Let me explain what is going on:

ent has an input port decalred (N-1 downto 0). 

In the port mapping, I create an aggregate (ip1 & ip0).

In VHDL, this defaults (0 to 1), but the port its mapping to is (1 downto 0). So mapping should be 0 -> 1 and 1 ->0 as per VHDL rules.

Unfortunately Vivado seems to think It can connect 0 -> 0 and 1 -> 1. This is NOT how VHDL mapping works, hence an elaboration bug.

10 Replies
Moderator
Moderator
642 Views
Registered: ‎03-16-2017

Re: Synthesis doesnt know difference between downto and to

Hi @richardhead,

I am looking into your source code. I will get back to you with the outcomes. 

 

Regards,

hemangd

 

Regards,
hemangd

Don't forget to give kudos and accept it as solution if your issue gets resolved.
0 Kudos
Scholar richardhead
Scholar
627 Views
Registered: ‎08-01-2012

Re: Synthesis doesnt know difference between downto and to

If I change the code to be more 1993 style (code still set as VHDL 2008), it works as expected. Only change is:

type slv_array_t is array(natural range <>) of std_logic_vector(7 downto 0);

Elaboration is:

noswap.PNG

So I assume this is a difference in the way Vivado is handling 2008 unconstrained arrays (and records, because in my real code I have an array of records as a port - and it also exhibits the same issue as #1)

0 Kudos
Scholar richardhead
Scholar
560 Views
Registered: ‎08-01-2012

Re: Synthesis doesnt know difference between downto and to

@hemangd

 

Any update on this?

0 Kudos
Moderator
Moderator
545 Views
Registered: ‎07-21-2014

Re: Synthesis doesnt know difference between downto and to

@richardhead

I used the code posted in your first reply and ran it in 2018.2 and I don't see any issue. Please let me know which version of Vivado you are using or if I missed anything.

VHDL_2008_elab.PNG

Thanks
Anusheel

0 Kudos
Scholar richardhead
Scholar
538 Views
Registered: ‎08-01-2012

Re: Synthesis doesnt know difference between downto and to

@anusheel

 

You have exactly the same problem as me. IP0 should connect to OP0, but it doesnt - it connect to OP1

0 Kudos
Scholar richardhead
Scholar
499 Views
Registered: ‎08-01-2012

Re: Synthesis doesnt know difference between downto and to

@anusheel

This is Vivado 2018.2

As you have shown, you are seing the same problem as me (please look at the paths all the way through the diagram). If you modify the type in the package (no other code mods), as per #3, the problem goes away (as I show in the picture inn #3, IP0 -> OP0, and IP1 -> OP1). This appears to be a bug in the way Vivado interprets VHDL2008 aggregates when done in a port map.

 

0 Kudos
Scholar richardhead
Scholar
427 Views
Registered: ‎08-01-2012

Re: Synthesis doesnt know difference between downto and to

@anusheel @hemangd

What is the status on reporting this bug?

0 Kudos
Moderator
Moderator
320 Views
Registered: ‎07-21-2014

Re: Synthesis doesnt know difference between downto and to

@richardhead

I have filed a CR for this issue.

Thanks
Anusheel

0 Kudos
Scholar richardhead
Scholar
177 Views
Registered: ‎08-01-2012

Re: Synthesis doesnt know difference between downto and to

@anusheel

Can you confirm if this has been fixed in the preview vivado builds? (I assume 2019.1)

0 Kudos
Moderator
Moderator
149 Views
Registered: ‎07-21-2014

Re: Synthesis doesnt know difference between downto and to

@richardhead

This CR is still under investigation. We should have some update on this CR in coming weeks.

Thanks
Anusheel 

0 Kudos