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toyona
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Registered: ‎09-29-2014

Synthesis fail due to a warning regarding tristate

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Hello~

Im really new at this so here goes:

Im using Xilinx ISE 8.2i . At my lab class, 3 versions of designing a simple ALU with only an adder and subtractor were given. Im trying out version 3 (which is safe and avoids bus contention) but it keeps showing me a warning:

WARNING:Xst:2183 - Unit ex_3c: the following tristate(s) are NOT replaced by logic (Please refer to Answer Record 20048 for more information): N1.


SOME MORE INFO: design target  is XC2C256-TQ144.

this is the code (Verilog 2001)and Ive uploaded the picture for the design I am
 following:

`timescale 1ns / 1ps
module Lab_M1_VL_01_XST_X8P2_CR2
(input wire EN, CIN, A, B,
output wire SUM, DIFFERENCE, OUT_BUS);
//INTERNAL SIGNALS
wire B_BAR, EN_BAR;
//DESIGN DESCRIPTION
//FULL ADDER
assign SUM = A ^ B ^ CIN;
//HALF SUBTRACTER
assign B_BAR = ~ B;
assign DIFFERENCE = A ^ B_BAR ^ 1'b1;
//TRI-STATE BUFFERS
assign EN_BAR = ~ EN;
assign OUT_BUS = EN? SUM : 1'bz;
assign OUT_BUS = EN_BAR? DIFFERENCE : 1'bz;
endmodule

I cant move forward because the synth keeps failing all though the syntax is fine. What do I do to solve this? 

 

Thanks in adavance.

Untitled picture.png
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1 Solution

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geoffbarnes
Explorer
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14,359 Views
Registered: ‎09-07-2011

Your right, it is logically equivalent - however CPLDs/FPGA typically do not directly support the "wired-or" like shown in your picture.    Instead, the synthesizer will try and emulate the same behaviour with muxes.    But it sounds like in this case XST might not be able to do that since this is on an output  (i.e due to yashp's 3rd bullet).

 

The quick answer is to use a mux :

 

assign OUT_BUS = EN ? SUM : DIFFERENCE;

 

 

View solution in original post

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6 Replies
yashp
Moderator
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9,076 Views
Registered: ‎01-16-2013
Hi,

There are four situations where XST is not able to replace a tristate by logic:

- The tristate is connected to a black box.
- The tristate is connected to the output of a block, and the hierarchy of the block is preserved.
- The tristate is connected to a top-level output.
- The "tristate2logic" constraint is set to "no" on the block where tristates are placed or on the signals to which tristates are connected.

Please resolve the multi-souce condition in your coding.

assign OUT_BUS = EN? SUM : 1'bz;
assign OUT_BUS = EN_BAR? DIFFERENCE : 1'bz;

Thanks,
Yash
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toyona
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Registered: ‎09-29-2014

 I still dont quite get it...

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muzaffer
Teacher
Teacher
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Registered: ‎03-31-2012
he means you have two different drivers to out_bus, you need to reduce them to one; maybe:
assign output_select = sel_out ? sum:difference;
assign out_bus = en ? output_select : 1'bz;
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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toyona
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Registered: ‎09-29-2014

Is that really the problem? Its not showing me the multiple drivers warning anyway. Besides, according to the code/logic, the tristates would not get activated at the same time so either the adder or the subtractor is supposed to drive the out_bus.

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geoffbarnes
Explorer
Explorer
14,360 Views
Registered: ‎09-07-2011

Your right, it is logically equivalent - however CPLDs/FPGA typically do not directly support the "wired-or" like shown in your picture.    Instead, the synthesizer will try and emulate the same behaviour with muxes.    But it sounds like in this case XST might not be able to do that since this is on an output  (i.e due to yashp's 3rd bullet).

 

The quick answer is to use a mux :

 

assign OUT_BUS = EN ? SUM : DIFFERENCE;

 

 

View solution in original post

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toyona
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Registered: ‎09-29-2014

Yeah, I tried that some time ago, seems like this is the only solution. Thanks~

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