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Visitor pradeepreddy
Visitor
733 Views
Registered: ‎02-20-2018

Synthesis of Block Design wrapper

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Did the synthesis flow in vivado 2017.2 for the creating Block Diagram in the following steps

 

1. Created Project

2. Created Block diagram

3. Added RTL Files 

4. Added RTL Module to the Block Diagram

5. Integrated RTL with IP Core.

6. Generated Block Design

7. Validated Design

8. Created HDL Wrapper

9. Saved Design

10. Run Synthesis.

 

But when running the synthesis, i did see args in the log file for synthesis command is <rtl_top_module>.tcl instead of <wrapper_bd>.tcl

So it is doing synthesis for only rtl top but not block design wrapper

Do i miss any steps in the process of this.

 

Please let me know.

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1 Solution

Accepted Solutions
Moderator
Moderator
997 Views
Registered: ‎09-15-2016

Re: Synthesis of Block Design wrapper

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Hi @pradeepreddy

 

Ideally it should show <wrapper_bd>.tcl in the args in the log file as long as your wrapper is set as top. Is your wrapper file set as top?

The steps being followed looks correct to my knowledge. Can you show the source hierarchy of your project?

 

Regards

Rohit

  

Regards
Rohit
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1 Reply
Moderator
Moderator
998 Views
Registered: ‎09-15-2016

Re: Synthesis of Block Design wrapper

Jump to solution

Hi @pradeepreddy

 

Ideally it should show <wrapper_bd>.tcl in the args in the log file as long as your wrapper is set as top. Is your wrapper file set as top?

The steps being followed looks correct to my knowledge. Can you show the source hierarchy of your project?

 

Regards

Rohit

  

Regards
Rohit
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

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