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dschussheim
Explorer
Explorer
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Registered: ‎06-08-2017

Synthesis replaces IBUFG with IBUF for clock input

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This is how I buffer an external clock into the FPGA global clock tree.

IBUFG #(.IBUF_LOW_PWR("FALSE"), // Low power="TRUE", Highest performance="FALSE"
        .IOSTANDARD("LVCMOS18"))  // Specify the input I/O standard
IBUFG_inst (.O(clk_out), // Clock buffer output
            .I(clk_in));      // Clock buffer input (connect directly to top-level port)

 When I synthesize the design I get this warning:

[Netlist 29-432] The IBUFG primitive 'clkINPUT0/IBUFG_inst' has been retargeted to an IBUF primitive only. No BUFG will be added. If a global buffer is intended, please instantiate an available global clock primitive from the current architecture.

Why does this happen? Does it matter?

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barriet
Xilinx Employee
Xilinx Employee
502 Views
Registered: ‎08-13-2007

Which FPGA family?

If I remember right, that was an one old way of doing effectively IBUF -> BUFG - and maybe making sure the placer gave you a GCLK input. Maybe in the original Virtex and Spartan-II days, but wouldn't swear to it.

IBUFG isn't a valid primitive type for 7 series - see UG953. So it looks like it is converting it to the closest thing (IBUF). And then expecting you to add the BUFG if you that's what you wanted... Why didn't it do it for you? - not sure but I suspect it is because there are a lot more options (BUFR, BUFH, BUFIO) that there used to be.

Cheers,

bt

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barriet
Xilinx Employee
Xilinx Employee
503 Views
Registered: ‎08-13-2007

Which FPGA family?

If I remember right, that was an one old way of doing effectively IBUF -> BUFG - and maybe making sure the placer gave you a GCLK input. Maybe in the original Virtex and Spartan-II days, but wouldn't swear to it.

IBUFG isn't a valid primitive type for 7 series - see UG953. So it looks like it is converting it to the closest thing (IBUF). And then expecting you to add the BUFG if you that's what you wanted... Why didn't it do it for you? - not sure but I suspect it is because there are a lot more options (BUFR, BUFH, BUFIO) that there used to be.

Cheers,

bt

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dschussheim
Explorer
Explorer
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Registered: ‎06-08-2017

I'm using a Kintex-7 device: xc7k160t-2ffg676.

wire clk_int;
//IBUF: Single-ended Input Buffer
IBUF#(.IBUF_LOW_PWR("FALSE"),  // Low power="TRUE", Highest performance="FALSE"
      .IOSTANDARD("LVCMOS18")) // Specify the input I/O standard
IBUF_inst (.O(clk_int), // Clock buffer output
           .I(clk_in)); // Clock buffer input (connect directly to top-level port)

// BUFG: Global Clock Simple Buffer
BUFG BUFG_inst (.O(clk_out), // 1-bit output: Clock output
                .I(clk_int)); // 1-bit input: Clock input

 This returns no synthesis warning, and should do what I want.

I guess I was using an old libraries guide. I got IBUFG from page 152 of the 7 series libraries HDL. I'll use the updated guide you mentioned. I didn't realize there was a newer one. Thanks.

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avrumw
Guide
Guide
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Registered: ‎01-23-2009

Take a look at this post on the IBUFG - there is no "real physical cell" called an IBUFG - it is simply a coding shortcut for an IBUF that (in earlier families) would give an error message if it was LOC'ed to anything other than a clock capable site. It is still legal to use the IBUFG in all technologies, but it is (and should be) mapped to an IBUF after synthesis.

Avrum