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Observer
Observer
3,142 Views
Registered: ‎08-05-2015

Synthesis stuck at one place

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Hi all, 

   My design synthesis is stuck at the following message place. Even after over night its still running. I took this design and ran in other system. In that it was completes the synthesis. I uninstalled and re-installed the vivado 15.4 tool in my system. But the issue is not solved. Even, already bit file generated design also stuck in this place. 

 

 

Thanks & Regards

Rajesh.M

 

 

---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 900 (col length:140)
BRAMs: 1090 (col length: RAMB18 140 RAMB36 70)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
INFO: [Synth 8-5580] Multithreading enabled for synth_design using a maximum of 2 processes.
Start Parallel Synthesis Optimization : Time (s): cpu = 00:06:58 ; elapsed = 00:07:09 . Memory (MB): peak = 1058.207 ; gain = 887.441

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Observer
Observer
4,015 Views
Registered: ‎08-05-2015

Hi,

  My problems was solved. Initially i uninstalled and re-installed the vivado tool. Though my problem was not solved and finally changed my OS(same windows version). Now my design is completely running to end. 

 

Thanks & Regards

Rajesh.M

 

Part Resources:
DSPs: 900 (col length:140)
BRAMs: 1090 (col length: RAMB18 140 RAMB36 70)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
INFO: [Synth 8-5580] Multithreading enabled for synth_design using a maximum of 2 processes.
Start Parallel Synthesis Optimization : Time (s): cpu = 00:27:46 ; elapsed = 00:28:16 . Memory (MB): peak = 1959.164 ; gain = 1788.453
---------------------------------------------------------------------------------
Start Cross Boundary Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-3917] design Top_Eth_Design has port sfp_tx_disable driven by constant 0

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9 Replies
Xilinx Employee
Xilinx Employee
3,134 Views
Registered: ‎08-01-2008

Your design using pretty high number of BRAMs . Are you sure you really need that much number of BRAMs. It may issue with your coding style .

I would recommend you to use Block Memory generator IP or use language template for BRAM inference and try synthesis again

Thanks and Regards
Balkrishan
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Scholar
Scholar
3,124 Views
Registered: ‎08-07-2014

Hi,

 

If your synthesis process isn't clean, then it would be meaningless to proceed to Impl.

 

You message contains very little info so as to guess the problem origin.

I see that you use DSPs and BRAMs. Are you instantiating Xilinx primitives for them or are they being inferred by the synth tool from your RTL?

 

You can recheck your RTL, the part where these memories are described/instiantiated.

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Observer
Observer
3,119 Views
Registered: ‎08-05-2015
HI, The same design is running in other system.

Regards
Rajesh M


Start Part Resource Summary
-----------------------------------------------------------------------------
Part Resources:
DSPs: 900 (col length:140)
BRAMs: 1090 (col length: RAMB18 140 RAMB36 70)
------------------------------------------------------------------------------
Finished Part Resource Summary
-----------------------------------------------------------------------------
INFO: [Synth 8-5580] Multithreading enabled for synth_design using a maximum of 2 processes.
Start Parallel Synthesis Optimization : Time (s): cpu = 01:23:08 ; lapsed = 01:24:28 . Memory (MB): peak = 1959.477 ; gain = 1788.723
-------------------------------------------------------------------
Start Cross Boundary Optimization
-------------------------------------------------------------------
WARNING: [Synth 8-3917] design Top_Eth_Design has port sfp_tx_disable driven by constant 0
INFO: [Synth 8-5545] ROM "refclk_stable_count" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
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Moderator
Moderator
3,113 Views
Registered: ‎09-15-2016

Hi @rajesh.zoho

 

Looks like issue is specific to your machine. Which OS you are using? Is that supported one?

Try enabling multithreading based on the no. of processors you have. Refer link below, page 7:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug904-vivado-implementation.pdf

 

Regards

Rohit

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Regards
Rohit
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Observer
Observer
3,106 Views
Registered: ‎08-05-2015

Hi, This is my system configuration. The design is complied two days before. facing this problem from yesterday. 

System.PNG
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Xilinx Employee
Xilinx Employee
3,101 Views
Registered: ‎08-01-2008
You may share your design so we can run at our end . This seems your local machine issue
Thanks and Regards
Balkrishan
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Moderator
Moderator
3,097 Views
Registered: ‎03-16-2017

Hi @rajesh.zoho

 

1. Can you try by applying tcl command "set_param general.maxThreads 8”  and then rerun the synthesis?

 

2. Also are you running synthesis with number jobs 8? If not, try with 8. 

 

now1.JPG

 

3. Also provide Vivado.log and provide synthesis log file if it completes on other machine. 

 

Regards,

hemangd

Regards,
hemangd

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Observer
Observer
3,096 Views
Registered: ‎08-05-2015
Hi,
I already mentioned, its was completely running in my test system. it was not design problem. may be vivado 15.4 tool or my system.

Thanks & Regards
Rajesh.M
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Observer
Observer
4,016 Views
Registered: ‎08-05-2015

Hi,

  My problems was solved. Initially i uninstalled and re-installed the vivado tool. Though my problem was not solved and finally changed my OS(same windows version). Now my design is completely running to end. 

 

Thanks & Regards

Rajesh.M

 

Part Resources:
DSPs: 900 (col length:140)
BRAMs: 1090 (col length: RAMB18 140 RAMB36 70)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
INFO: [Synth 8-5580] Multithreading enabled for synth_design using a maximum of 2 processes.
Start Parallel Synthesis Optimization : Time (s): cpu = 00:27:46 ; elapsed = 00:28:16 . Memory (MB): peak = 1959.164 ; gain = 1788.453
---------------------------------------------------------------------------------
Start Cross Boundary Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-3917] design Top_Eth_Design has port sfp_tx_disable driven by constant 0

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