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Visitor rostwang
Visitor
158 Views
Registered: ‎12-05-2018

Synthesis takes lots of memory and eventually failed

Hi everyone,

I am using Vivado 2015.2 to synthesis a design. the synthesis takes around 24 hours and at the final step of Translating synthesized netlist, it shows :

"INFO: [Project 1-571] Translating synthesized netlist
ERROR: [Common 17-179] Fork failed: Cannot allocate memory"

in this synthesis process the memory can go up to 75G of memory start from Technology Mapping , is there any condition that can lead to heavy memory usage?

I am using default directive setting.

 

thanks,

rost.

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6 Replies
Moderator
Moderator
131 Views
Registered: ‎03-16-2017

Re: Synthesis takes lots of memory and eventually failed

Hi @rostwang,

 

1. Use latest version of Vivado which is 2018.2 because lots of changes have been done with the tool and it may help you to overcome your memory allocation issue. 

2. If you are using big chunks of RAM try to reduce the indexes of it and check.

3. Try by reducing index values of arrays if any. 

4. Also try to use distributed RAM by applying its attribute. Check UG 901 for more info. on it.

Regards,
hemangd

Don't forget to give kudos and accept it as solution if your issue gets resolved.
Visitor rostwang
Visitor
117 Views
Registered: ‎12-05-2018

Re: Synthesis takes lots of memory and eventually failed

Hi @hemangd,

Thanks for the suggestion and I will see if we have latest version to try.

for the memory in my design, originally I Have two 4822 bit wide and 16 entry depth memory. After the first round, I found it is too wide to fit as BRAM in vivado, so I break it down to 16 of 32 bit wide and 256 entry depth memories.  Can I say my original approach is better in synthesis?

for the 4th point, is it a constraint file that I should have? I will check UG 901 and see.

 

Thanks,

rost

 

 

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Xilinx Employee
Xilinx Employee
103 Views
Registered: ‎04-19-2010

Re: Synthesis takes lots of memory and eventually failed

One other thing to try is to see if the timing constraints are causing a problem.  Try running the design without any timing and see if that allows the design to complete.

Moderator
Moderator
83 Views
Registered: ‎03-16-2017

Re: Synthesis takes lots of memory and eventually failed

Hi @rostwang,

>>After the first round, I found it is too wide to fit as BRAM in vivado, so I break it down to 16 of 32 bit wide and 256 entry depth memories. 

Try to reduce these values and check if it works or not.

 

UG 901 , page 55, will show the RAM style , you can try by applying (* ram_style = “distributed” *)  which will Instructs the tool to infer the LUT RAMs. 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug901-vivado-synthesis.pdf

 

Regards,
hemangd

Don't forget to give kudos and accept it as solution if your issue gets resolved.
Visitor rostwang
Visitor
65 Views
Registered: ‎12-05-2018

Re: Synthesis takes lots of memory and eventually failed

One other question for VIVADO 2018, is it available to download with our current licenses or it is required a new license purchase?

I asked customer services but they ask me to ask here.

 

thanks,

rost

 

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Moderator
Moderator
37 Views
Registered: ‎03-16-2017

Re: Synthesis takes lots of memory and eventually failed

Hi @rostwang,

Open a new thread for your license related query since this is synthesis board. Create a new thread in installation and licensing board. 

And if your synthesis related query has been resolved  based on my previous suggestions, please close the thread by marking it as accepted solution. Else we can debug this further.

 

 

Regards,
hemangd

Don't forget to give kudos and accept it as solution if your issue gets resolved.
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