10-10-2017 08:35 AM
Synthesis operation crashes, outputting following messages:
[INFO] Looking for combinational gated clock conversion opportunities (AND/OR/NAND/NOR) on gated clock 'n_0_689'
Abnormal program termination (11)
Please check '/home/bud/projects/AmalteaFpgaDirk/mlx75320BA/digital/processing/fpga/hs_err_pid11308.log' for details
bash-4.1$ Parent process (pid 11308) has died. This helper process will now exit.
hs_err_pid11308.log is attached
There is no net n_0_689 in synthesized design with neither rebuilt nor full flatten hierarchy. How can i determine which place in design causes error to work around it?
10-12-2017 04:33 AM
Unfortunately i can't share project RTL until there NDA is not signed.
10-12-2017 04:55 AM
10-12-2017 05:14 AM
To avoid crash, try to change the flatten_hierarchy to none.
Also, if you can debug and understand at which module this issue got triggered then put a KEEP_HIERARCHY attribute to that module to block clock conversion and see if tool completes synthesis.
Also, what happens when you disable gated clock conversion under synthesis settings?
01-16-2018 05:19 AM
Hi There is a bug with the synthesis tool which means that your synthesis may crash.
As an ASIC to FPGA engineer I have suffered many hours of wasted time due to problems with synthesis tool not dealing well with gated clock latches.
Please see this post I have just written.
01-16-2018 09:51 PM