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Visitor
Visitor
2,330 Views
Registered: ‎02-21-2017

Synthesis with gated clock conversion crashes

Hello!

 

Synthesis operation crashes, outputting following messages:

 

[INFO] Looking for combinational gated clock conversion opportunities (AND/OR/NAND/NOR) on gated clock 'n_0_689'
Doing HARTGatedClock::extractGatedClockEnableWithNlopt
Abnormal program termination (11)
Please check '/home/bud/projects/AmalteaFpgaDirk/mlx75320BA/digital/processing/fpga/hs_err_pid11308.log' for details
bash-4.1$ Parent process (pid 11308) has died. This helper process will now exit.

 

hs_err_pid11308.log is attached

 

There is no net n_0_689 in synthesized design with neither rebuilt nor full flatten hierarchy.  How can i determine which place in design causes error to work around it?

 

Thanks,

Bogdan

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7 Replies
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Xilinx Employee
Xilinx Employee
2,289 Views
Registered: ‎02-16-2014

Hi @bud_melexis

 

Is it possible to share testcase to further debug this issue?

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Visitor
Visitor
2,269 Views
Registered: ‎02-21-2017

Hello Manusha,

 

Unfortunately i can't share project RTL until there NDA is not signed. 

 

Regards,

Bogdan

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Moderator
Moderator
2,261 Views
Registered: ‎01-16-2013

Hi,

Is this ASIC design for FPGA prototyping? Or you have designed this only for FPGA?

If it's only FPGA specific then I guess it's better to avoid clock gating using combination logic, you can use the UG949 to handle better clock gating using proper clock buffers.

Thanks,
Yash
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Moderator
Moderator
2,259 Views
Registered: ‎07-21-2014

@bud_melexis

 

To avoid crash, try to change the flatten_hierarchy to none. 

Also, if you can debug and understand at which module this issue got triggered then put a KEEP_HIERARCHY attribute to that module to block clock conversion and see if tool completes synthesis.

 

Also, what happens when you disable gated clock conversion under synthesis settings? 

 

Thanks,

Anusheel

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Xilinx Employee
Xilinx Employee
2,228 Views
Registered: ‎09-04-2017

Hi,

  Can you try with 2017.3. I see the design was run with 2017.2

 

Thanks,

Nithin

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Adventurer
Adventurer
1,837 Views
Registered: ‎02-08-2016

Hi There is a bug with the synthesis tool which means that your synthesis may crash.

 

 

As an ASIC to FPGA engineer I have suffered many hours of wasted time due to problems with synthesis tool not dealing well with gated clock latches.

 

Please see this post I have just written.

https://forums.xilinx.com/t5/Synthesis/Synthesis-Bug-Vivado-Synthesis-Tool-fails-during-gated-clock/td-p/822426

 

Cheers Simon

 

 

 

GOODSYNTH.png
GoodELAB.png
badelab.png
Synthfails.png
SYNTHNOCONVERT.png
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Moderator
Moderator
1,824 Views
Registered: ‎07-21-2014

@simonh_bwt

 

I can see that @pulim is already working on this reported crash issue. Thanks for reporting this issue.

 

Thanks,

Anusheel

 

 

 

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