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Registered: ‎08-12-2009

Synthesizing adders into DSP48

In an IIR filter design in a Spartan 3A DSP, some of the adders are synthesized into DSP48s, others are synthesized into logic.

All of the adder result signals have the dsp_style attribute set to DSP48:

    attribute syn_dspstyle of W, WxA12, WxA12D, WDxB12, WDxB12D, HPFOUTINT: signal is "dsp48";

The adder code is:

    WxA12D       <= conv_signed(WxA1, WxA12D'length) + conv_signed(WxA2D, WxA12D'length);                                 -- Synthesized into logic
    W                    <= conv_signed(InxS, W'length) - WxA12D(WxA12D'high-3 downto WxA12D'high-3 - W'length +1);  -- Synthesized into DSP48s

 

What factors can cause the synthesizer to ignore the attribute and implement some adders in logic?

I use VHDL, Synplify  pro 9.2 and a Spartan-3A DSP part. Only about 50% of the DSP48s and the logic are used, so no resource shortage.

 

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