02-27-2021 05:35 AM
I came to understand that Vivado doesn't support synthesis of Systemverilog classes.
A quick search shows that questions about this have been raised as far back as 2016. So it's clear that little (if not zero) effort has been invested in that direction for the past 5 years.
Being an industry leader comes with a responsibility - so I feel that Xilinx should invest more in enabling such important features (even if it doesn't sell more chips). Or at least be 100% forefront and state that this feature ( along with other "advanced" constructs ) will never be implemented.
03-02-2021 01:54 PM
What sort of support from SystemVerilog classes are you looking for?
Class objects are pretty much, by definition, dynamic constructs. Mapping these dynamic constructs to a static set of hardware is going to be tricky. The most likely way the this would be solved would be to restrict the class use case (perhaps quite severely) just to be able to map the descriptions to hardware.
I can only think of a few things within SystemVerilog classes that could be useful in the context of Synthesis. One is parameterized functions - but (from your other thread) there's other Synthesizable ways of accomplishing this goal. (Perhaps not as cleanly - I'll give you that).
But I struggle to think of other things within a SystemVerilog class that would be useful to Synthesis. What else can you think of?
03-04-2021 04:34 AM
I was thinking about parametrized functions...
From all the reading I did and examples I saw - using classes is "the correct way" to implement parametrized functions.
The interface approach works - but it's a workaround due to lack of support for classes.