UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer kirito0816
Observer
186 Views
Registered: ‎11-26-2018

Taking long time when loading nets in "setup debug"

Hello,

I am using Vivado 2016.4 to do a VHDL-Verilog project. If I add the debug in VHDL part, like (attribute mark debug), it works fine. But when I add debug core in Verilog part, (mark debug = true), it is blocked and takes about 10 minutes to load just 1 net in "set up debug" process. I wonder if this matter is related to "Target language" or "cross language design". Thank you.

11.PNG22.PNG33.PNG44.PNG

0 Kudos
5 Replies
Xilinx Employee
Xilinx Employee
141 Views
Registered: ‎02-27-2019

回复: Taking long time when loading nets in "setup debug"

Hi @kirito0816 ,

Could you help me do a test that you choose Verilog and have a try? As for Target language, you can refer to AR63996:

The Target Language setting is used to:

  • Deliver IP core synthesizable source in the desired language if both languages are available. If only one language is available, the Target Language setting is ignored and the sources are delivered in the available HDL language.
  • Deliver instantiation template in the desired language.
-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Xilinx Employee
Xilinx Employee
117 Views
Registered: ‎05-14-2008

Re: Taking long time when loading nets in "setup debug"

I suggest try with the latest Vivado version.

-vivian

0 Kudos
Observer kirito0816
Observer
107 Views
Registered: ‎11-26-2018

回复: Taking long time when loading nets in "setup debug"

Thank you very much. I tried to change the target language, but the problem is still there. Then I tried to delete the VHDL debug core and only use the Verilog debug core.  It works faster.

0 Kudos
Observer kirito0816
Observer
106 Views
Registered: ‎11-26-2018

Re: Taking long time when loading nets in "setup debug"

Ok, thank you.

0 Kudos
Xilinx Employee
Xilinx Employee
94 Views
Registered: ‎05-14-2008

回复: Taking long time when loading nets in "setup debug"

What are the VHDL debug core and Verilog debug core? Are they Xilinx IP or your own source files?

Do they have any connections with each other?

-vivian

0 Kudos