06-03-2019 06:11 PM
I am using Vivado 2016.4 to do a VHDL-Verilog project. If I add the debug in VHDL part, like (attribute mark debug), it works fine. But when I add debug core in Verilog part, (mark debug = true), it is blocked and takes about 10 minutes to load just 1 net in "set up debug" process. I wonder if this matter is related to "Target language" or "cross language design". Thank you.
06-10-2019 02:02 AM
Hi @kirito0816 ,
Could you help me do a test that you choose Verilog and have a try? As for Target language, you can refer to AR63996:
The Target Language setting is used to:
06-11-2019 07:56 PM
Thank you very much. I tried to change the target language, but the problem is still there. Then I tried to delete the VHDL debug core and only use the Verilog debug core. It works faster.
06-11-2019 11:52 PM
What are the VHDL debug core and Verilog debug core? Are they Xilinx IP or your own source files?
Do they have any connections with each other?