cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor
Visitor
542 Views
Registered: ‎03-19-2015

The value of not initialized signal

Jump to solution

 

Why Vivado with that kind of RTL code:

signal Q : std_logic_vector(0 downto 0); --not initialized
    
begin
 
    FDPE_RE_PROC: process(C, PRE)
    begin
        if (PRE = '1') then
            Q <= (others => '1');
        elsif (rising_edge(C)) then
            if (CE = '1') then
                Q <= D;
            end if;
        end if;
    end process;

create:

  FDPE \Q_reg[0] // default INIT = 1
       (.C(C),
        .CE(CE),
        .D(D[0]),
        .PRE(PRE),
        .Q(Q[0]));

instead of:

  FDPE (#
   .INIT(1'b0)
 ) \Q_reg[0] 
       (.C(C),
        .CE(CE),
        .D(D[0]),
        .PRE(PRE),
        .Q(Q[0]));

The default value of uninnitialized signal should not be '0' on Xilinx [1] ? Why Vivado change uninitialized (0) value to value (1 - default FDPE INIT value) in this case? Is 0 value wrong or may cause maltfunction on hardware side? Please help me understand this.

Thanks for your explanation.

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Guide
Guide
333 Views
Registered: ‎01-23-2009

Re: The value of not initialized signal

Jump to solution

So I assume that using INIT value of '0' when infered register with (a)synchronous preset/set with non-initialized register signal is just that correct as using value of '1' in the same case. It is a matter of arbitrary choice of synthesis tool - not specified by any HDL/synthesis standard or resulting from any pragmatic reasons, if I understand problem of this matter correctly.

You have to understand that RTL is used not only for FPGA, but also for ASIC design. In an ASIC, when the ASIC powers up, any flip-flops in the design are truly in an unknown state - they will either be 0 or 1, but the value may be different from flip-flop to flip-flop and even from power cycle to power cycle. As a result, the only mechansim of getting an ASIC into a known initial state is through a global reset - there is no concept of "initial value".

Since an FPGA goes through a configuration cycle before "time 0" of your RTL design, the state of all flip-flops is set as part of the configuration cycle. If your RTL is "technology agnostic" and doesn't count on the FPGA initialization (i.e. your RTL code will work in both an ASIC and an FPGA), then if the RTL code has no explicit reset, then the value of the FF at powerup is truly don't care - so in an FPGA the tools can choose either value (so it chooses 0). If the ASIC code has an explicit reset, then the FPGA synthesis tool is still free to choose, so it chooses the value of the explicit reset - there is no hard "need" for this, but there is also no reason why not, so it does.

The concept of intializing the underlying signal/reg/logic has no meaning in ASIC design, and is, in fact, highly discouraged, since the real hardware will come up in any state - if you do initialization at declaration, then this will affect your simulation, but won't change the fact that the FF is unknown in hardware. This can lead to simulation/synthesis mismatches (which is why it is discouraged).

However, in FPGA, since the initial value of the FF can be set by the synthesis tool, the synthesis vendors have added functionality to have the initial value set at signal/logic/wire declaration become the INIT value of the flip-flop. This enables functionality that is not possible in an ASIC - setting the "time 0" (essentially powerup) value of a flip-flop without an explicit reset. This allows you more capability to design systems that have fewer explicit resets - explicit resets cost routing and performance in an FPGA. Since it is implemented the way (the declaration initialization value becoming the INIT value of the flip-flop), RTL simulation and the real hardware will behave the same way - at "time 0", which is both the start of the RTL simulation and the equivalent of the end of the configuration cycle in the FPGA, the value of the flip-flop will be known and the same in simulation and hardware.

Avrum

View solution in original post

9 Replies
Highlighted
532 Views
Registered: ‎06-21-2017

Re: The value of not initialized signal

Jump to solution

If you want th eintl value to be '1', declare it. 

signal Q : std_logic_vector(0 downto 0)  := (OTHERS => '1');

It is goodddddddddddddddddddactice to declare initial values for your signals.  The synthesis tool will default to '0' if not told otherwise, but the simulator will default to UNDEFINED.

0 Kudos
Highlighted
Visitor
Visitor
516 Views
Registered: ‎03-19-2015

Re: The value of not initialized signal

Jump to solution

I know I can declare whatever initial value I like, but the question is quite different:

Why Vivado initialized non-initialized signal value by using reset/set/preset/clear value from register but not 0 (which is default power-up initial value in Xilinx technologies)?

Best Regards

0 Kudos
Highlighted
Guide
Guide
482 Views
Registered: ‎01-23-2009

Re: The value of not initialized signal

Jump to solution

Why Vivado initialized non-initialized signal value by using reset/set/preset/clear value from register but not 0 (which is default power-up initial value in Xilinx technologies)?

Because it does.

The INIT value of a flip-flop is chosen by the following rules (in order):

  • Using the initial value of the underlying signal/reg/logic (as specified during the declaration of the signal/reg/logic, or through an initial update)
  • If no initialization exists, the value of the reset is used (assuming the flip-flop has a recognizable  asynchronous preset/clear)
    • This behavior does not appear to be documented in the Vivado synthesis guide, but does appear in the XST synthesis guide - UG626, v14.4, p. 63)
    • I am virtually certain that this will occur in Vivado (as you are seeing) even though it isn't clearly stated
    • I am not certain what happens if the reset is synchronous as opposed to asynchronous - I thought the behavior would be the same, but UG626 specifically mentions asynchronous presets
  • If neither of the above exists, then the default is 0

Your code clearly falls into the 2nd case.

Avrum

Highlighted
Scholar
Scholar
458 Views
Registered: ‎06-20-2017

Re: The value of not initialized signal

Jump to solution

@avrumw wrote:

Why Vivado initialized non-initialized signal value by using reset/set/preset/clear value from register but not 0 (which is default power-up initial value in Xilinx technologies)?

Because it does.

The INIT value of a flip-flop is chosen by the following rules (in order):

  • Using the initial value of the underlying signal/reg/logic (as specified during the declaration of the signal/reg/logic, or through an initial update)
  • If no initialization exists, the value of the reset is used (assuming the flip-flop has a recognizable  asynchronous preset/clear)
    • This behavior does not appear to be documented in the Vivado synthesis guide, but does appear in the XST synthesis guide - UG626, v14.4, p. 63)
    • I am virtually certain that this will occur in Vivado (as you are seeing) even though it isn't clearly stated
    • I am not certain what happens if the reset is synchronous as opposed to asynchronous - I thought the behavior would be the same, but UG626 specifically mentions asynchronous presets
  • If neither of the above exists, then the default is 0

Your code clearly falls into the 2nd case.

Avrum


The last time I tested Vivado, a signal uninitialized during its declaration would be initialized with the value of its synchronous set/reset, or to 0 if there were no set/reset. 

This of course is not documentation but I have tested this, and wanted to lend support to your view.

Mike
Highlighted
Visitor
Visitor
377 Views
Registered: ‎03-19-2015

Re: The value of not initialized signal

Jump to solution

@avrumw wrote: Because it does.

So I assume that using INIT value of '0' when infered register with (a)synchronous preset/set with non-initialized register signal is just that correct as using value of '1' in the same case. It is a matter of arbitrary choice of synthesis tool - not specified by any HDL/synthesis standard or resulting from any pragmatic reasons, if I understand problem of this matter correctly.

0 Kudos
Highlighted
Scholar
Scholar
361 Views
Registered: ‎08-01-2012

Re: The value of not initialized signal

Jump to solution

I think if you dont specify a value, then you clearly do not care about it. Hence why should it matter if it is '0' or '1'. The init value in VHDL is 'U' for std_logic values, which then must be given a meaningful value at some point later in time. This maintains sim/synth match.

However, if you used some explicit type, like bit, boolean or natural, I would expect it to always power up '0'/false/0, as this is the default initial value for these types. If it didnt, then sim/synth would missmatch and be a bug if it didnt.

0 Kudos
Highlighted
Guide
Guide
334 Views
Registered: ‎01-23-2009

Re: The value of not initialized signal

Jump to solution

So I assume that using INIT value of '0' when infered register with (a)synchronous preset/set with non-initialized register signal is just that correct as using value of '1' in the same case. It is a matter of arbitrary choice of synthesis tool - not specified by any HDL/synthesis standard or resulting from any pragmatic reasons, if I understand problem of this matter correctly.

You have to understand that RTL is used not only for FPGA, but also for ASIC design. In an ASIC, when the ASIC powers up, any flip-flops in the design are truly in an unknown state - they will either be 0 or 1, but the value may be different from flip-flop to flip-flop and even from power cycle to power cycle. As a result, the only mechansim of getting an ASIC into a known initial state is through a global reset - there is no concept of "initial value".

Since an FPGA goes through a configuration cycle before "time 0" of your RTL design, the state of all flip-flops is set as part of the configuration cycle. If your RTL is "technology agnostic" and doesn't count on the FPGA initialization (i.e. your RTL code will work in both an ASIC and an FPGA), then if the RTL code has no explicit reset, then the value of the FF at powerup is truly don't care - so in an FPGA the tools can choose either value (so it chooses 0). If the ASIC code has an explicit reset, then the FPGA synthesis tool is still free to choose, so it chooses the value of the explicit reset - there is no hard "need" for this, but there is also no reason why not, so it does.

The concept of intializing the underlying signal/reg/logic has no meaning in ASIC design, and is, in fact, highly discouraged, since the real hardware will come up in any state - if you do initialization at declaration, then this will affect your simulation, but won't change the fact that the FF is unknown in hardware. This can lead to simulation/synthesis mismatches (which is why it is discouraged).

However, in FPGA, since the initial value of the FF can be set by the synthesis tool, the synthesis vendors have added functionality to have the initial value set at signal/logic/wire declaration become the INIT value of the flip-flop. This enables functionality that is not possible in an ASIC - setting the "time 0" (essentially powerup) value of a flip-flop without an explicit reset. This allows you more capability to design systems that have fewer explicit resets - explicit resets cost routing and performance in an FPGA. Since it is implemented the way (the declaration initialization value becoming the INIT value of the flip-flop), RTL simulation and the real hardware will behave the same way - at "time 0", which is both the start of the RTL simulation and the equivalent of the end of the configuration cycle in the FPGA, the value of the flip-flop will be known and the same in simulation and hardware.

Avrum

View solution in original post

Highlighted
274 Views
Registered: ‎01-08-2012

Re: The value of not initialized signal

Jump to solution

To be more explicit: in VHDL, an uninitialised value will take the leftmost value of that type.  For bit, this is 0.  For std_logic, this is 'U'.  For boolean, this is FALSE.  For natural, this is 0.  For a constrained integer (e.g. "integer range a to b"), this is the leftmost end of the range ("a").  For an unconstrained integer, this is (typically) -2**31 (which can be a trap for the unwary).

0 Kudos
Highlighted
272 Views
Registered: ‎01-08-2012

Re: The value of not initialized signal

Jump to solution

(That was in reply to Richard's post.)

0 Kudos