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nixiebunny
Contributor
Contributor
742 Views
Registered: ‎01-26-2009

There is no warning of undriven signal in VHDL design

Grr. I just wasted about 12 hours trying to find why my spectrometer design wouldn't implement fully in Vivado 2020.2 for Windows.

There was a signal defined, and it was tied to an input of its destination module. however, I hadn't defined its output port in the signal source module, so the signal was undriven in the top level VHDL code. A simple oversight, but one that should make the synthesis tool grind to screeching halt.

I got zero warnings or INFOs about the undriven signal in my VHDL code that caused my design to completely fail.

I got 200 oh-so-helpful warnings about undriven signals in the RFSoC data converter module, which is information that is of little interest to me, since I don't have any control over those warning messages.

Can you please please fix the warning system to tell me about things that matter to me, instead of things that don't matter?

 

8 Replies
furia
Observer
Observer
564 Views
Registered: ‎05-20-2010

Same problem here.

@Xilinx developers, do something.

 

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furia
Observer
Observer
553 Views
Registered: ‎05-20-2010

OK, I found workaround. In synth_design use the -verbose option and look for phrase: "does not have driver".

Maybe this can help you.

Regards,

Jerzy Gbur

 

dpaul24
Scholar
Scholar
548 Views
Registered: ‎08-07-2014

@all,

There was a signal defined, and it was tied to an input of its destination module. however, I hadn't defined its output port in the signal source module, so the signal was undriven in the top level VHDL code. A simple oversight, but one that should make the synthesis tool grind to screeching halt.

This is why functional verification through design simulation exists. The problem could have been caught there without having to go to the Synthesis stage.

 

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furia
Observer
Observer
455 Views
Registered: ‎05-20-2010

Man,

In your way synthesis software shouldn't generate any warnings.
This is weak argument.
Synthesizer has to generate warnings when something could go wrong. That's why compilers/synthesizers produce warnings.

Regards,

Jerzy

 

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bruce_karaffa
Scholar
Scholar
436 Views
Registered: ‎06-21-2017

A signal that is undriven is basically a constant.  It can be synthesized.  Even if Vivado throws a warning, most large designs have thousands of warnings.  Unless you know what you are looking for in the warnings, it is easy to miss this. 

dpaul24
Scholar
Scholar
432 Views
Registered: ‎08-07-2014

@furia ,

Perhaps one day you will understand the benefit of functional verification using simulation and not leaving everything to the synthesis engine to report all the inadvertent errors done during RTL description of the design. Till then all the best!

Also as mentioned above, synthesis issues many many warnings which can be ignored (depends) for successful bitstream generation.

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furia
Observer
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Registered: ‎05-20-2010

Hello @dpaul24 ,

Let's summarize,

@nixiebunny  has a problem because there are no warnings about uncontrolled signals during synthesis.

I suggested that he use the "-verbose" switch, You said use the simulator.

I don't know which way is faster, in solving this problem.

But to claim that the lack of this warning in the basic report is cool, is strange.

I also don't know where you got the idea that I don't appreciate verification tools.

The question from @nixiebunny was about warnings.

Regars,

Jerzy

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dpaul24
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Registered: ‎08-07-2014

@furia , I also don't know where you got the idea that I don't appreciate verification tools

Sorry for this to you, I got lost with the cascade of replies and thought that you are the OP. @nixiebunny jst started the thread and then did not come back again for any clarifications.

And you got me all wrong here -

In your way synthesis software shouldn't generate any warnings.
This is weak argument.

Next what to do or can be done in the following cases-

1. undriven inputs: Simulation should be able to catch it because these will be flagged as Xs by the simulator tool. So you immediately know that something has gone wrong even before proceeding to the synthesis stage. Since the OP talks about an undriven input hence was my argument for simulation. Lint checks can catch such errors during design compilation but they are almost non-existent in the FPGA domain.

2.undriven outputs: Normally synthesis tool will report this as a Warning. But they are most probably optimized away during opt_design and so you shouldn't find them anymore in your implemented design.

 

Again coming back to another comment of yours....

Synthesizer has to generate warnings when something could go wrong. That's why compilers/synthesizers produce warnings.

Yes they do generate Warning messages, one has to look closely inside the synthesis log file and not just at the limited verbose messages at the Vivado console window after a synthesis run.

In previous versions of Vivado synthesis tool, it was also possible to set the severity level of the messages, so that Warnings are reported as Errors. I do not know if it is still true.

set_msg_config -id "<the unique message ID>" -new_severity "ERROR"

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