04-30-2013 04:17 AM
I have my FPGA design working correctly and with all the timing constraints met.
I need to generate a library (a ngc file) of one of the components of my design to use it as a black box or core. I do it selecting the component as the top module of the design and unchecking the Add I/O Buffers option of the Xilinx Specific Options, and I obtain the ngc file implementing the design.
Then, on a copy of the original ISE project, I remove the source files of this component and I add the ngc file in the project.
The tools takes everything correctly, the Block Rams etc., but the design does not meet the timing constraints.
Both designs are similar. The unique difference is that one has the source code and the other one has only the ngc file.
Which could be the reason to obtain different timing results?
I am a little bit lost. Must I generate the NGC file with another option or something?
Thanks in advance.
10-31-2013 02:12 PM
I am in a very similar situation. Under ISE I have a working project in which I would like to replace several of the source code VHDL files called directly by the top-most VHDL file with their respective ngc versions. I have created the ngc files of interest with the Add I/O Buffers diasbled and then instantiated them in place of the VHDL files.
The timing of the project with the ngc modules is not met at all (the timing score goes from about ~5,500 to ~24,000,000).
Interestingly the number of initialy unrouted elements drops by about 7% for the project with the ngc module.
1) Is there a remedy for this?
2) Any specific synthesis options need to be selected?
3) Do the optimization tools handle optimizations accross multiple ngc modules well? (In the past I used single custom made ngc modules in smaller projects and all seemed fine)
Thank you for your help and time.
11-05-2013 03:48 AM
11-07-2013 01:55 AM
To debug this further could you please send me the .TWX & .PAR report for both the projects?