We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Registered: ‎07-21-2014

UltraFast Design Methodology Overview – Improve RTL Coding

Xilinx has created comprehensive UltraFast Design Methodology Guides that cover key principles, specific do's and don'ts, best practices, and ways to avoid pitfalls. In some topics, Xilinx provide real life use cases to illustrate concepts. The methodologies presented is a reflection of user experiences and learning gained from system development inside and outside of Xilinx. 


The RTL Coding Guideline section outlines the best practices in RTL coding techniques to ease timing closure, and the overall impact of the timing constraints at the synthesis level with a correlation to better timing closure.


Download the new UltraFast High-Level Design Methodology Guide today!