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Observer audriusa
Observer
655 Views
Registered: ‎01-25-2018

Unable to control the write order of the Vivado HLS Axis stream

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I need to write a HLS Axis stream module that reads and writes much more data than can be simply stored in some internal buffer. For this, I implemented the main function that reads from axis stream and then writes to the axis stream. The algorithm almost works but for some reason the order in which writes are made into the output stream does match the expected order.

The function calls three other functions (one of them in a loop). Complex_processing both reads and writes data, others only write to the output B. Regardless what I do, the output that comes from the last function (finish_frame) is written first, and the output from other functions follow in obviously wrong order. The complex_processing function is obviously the slowest one, but I really need to wait till it finishes before writing the closing sequence.

The output parameter initially was the hls::stream and writing the output in a wrong order. Thinking it may help I have replaced it by pointer, writing the way B[addr++]=value. Be it array, it would have elements in right order, but the output from the module still comes out the tail first. I have tried to place #pragma HLS protocol fixed into the function but this have not changed anything. 

The only working solution I have found so far is to write all output into C array, and then write the array to the output stream in loop at the end of the module call. This works, and HSL now understands that the array index exists for the reason in the assignment statement. However this requires storing all results of the single module call into array, multiple megabytes. I do not think there is not enough memory on FPGA to buffer this way.

Is it possible ensure in high level synthesis that the functions writing the output are executed in the order they are called, to produce the expected output in the agreed format. 

 

void example(hls::stream<axi_input> &A, axi_output * B) {
#pragma HLS INTERFACE axis port=A
#pragma HLS INTERFACE axis port=B depth=50000
	write_header(B);
	for (int superRow = 0; superRow < 800; superRow++) {
          complex_processing(B);
	}
	finish_frame(B);
}

 

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Observer audriusa
Observer
505 Views
Registered: ‎01-25-2018

Re: Unable to control the write order of the Vivado HLS Axis stream

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The answer to this question is, when the buffer is close to full, write it to the output (once) and then exit the module by passing the control to the end of its main function (return statement within the code seems not working properly). If new data appears, you will re-enter from the beginning and be able to read more data reusing the same buffer. Any state, if such exists, can be remembered in global variables and so preserved as we exit and re-enter the module. The subsequent buffer writes will follow in the expected order. 

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4 Replies
Teacher xilinxacct
Teacher
591 Views
Registered: ‎10-23-2018

Re: Unable to control the write order of the Vivado HLS Axis stream

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@audriusa

a 'stream' by nature is 'first in first out'. You are responsible to put things on the stream in the order you wish them.

You may want to use some other interface if more suitable, OR put some 'order' information in the stream record, that you can then recover the 'order' after the fact.

Hope that helps

If so, please mark as 'solution accepted'... Kudos also welcomed :-)

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Observer audriusa
Observer
577 Views
Registered: ‎01-25-2018

Re: Unable to control the write order of the Vivado HLS Axis stream

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@xilinxacct

If executed on a usual PC platform, after being compiled with the ordinary compiler, the code would definitely put the data into the stream in the expected order. All question is about how achieve the same goal for HLS.

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Teacher xilinxacct
Teacher
570 Views
Registered: ‎10-23-2018

Re: Unable to control the write order of the Vivado HLS Axis stream

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@audriusa

Yes, and no... If you do a single threaded application, the stream would be read/written is a repeatable order... If that application is parallel (as the FPGA 'can' be), the timing of when the reads/writes are done is not ordered.

Hope that helps

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Observer audriusa
Observer
506 Views
Registered: ‎01-25-2018

Re: Unable to control the write order of the Vivado HLS Axis stream

Jump to solution

The answer to this question is, when the buffer is close to full, write it to the output (once) and then exit the module by passing the control to the end of its main function (return statement within the code seems not working properly). If new data appears, you will re-enter from the beginning and be able to read more data reusing the same buffer. Any state, if such exists, can be remembered in global variables and so preserved as we exit and re-enter the module. The subsequent buffer writes will follow in the expected order. 

0 Kudos