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1,090 Views
Registered: ‎06-26-2019

Unsupported Dual Port Block Ram Template (Vivado Synthesis)

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 I got a problem when I synthesis code below

reg [ROW_LENGTH-1:0] fifo [FIFO_ROWS-1:0];

wire [ROWPTR_SIZE-1:0] fiforow_ptr_e8 [`ETMA7_FIFO_ROW_BYTES-1:0];

wire [ROW_LENGTH-1:0] fifodata_e8;

wire [`ETMA7_FIFO_ROW_BYTES-1:0] fifobyte_active_e8;

generate

    for (i = 0; i < `ETMA7_FIFO_ROW_BYTES; i = i + 1) begin : fifo_column

      always @(posedge clk_g)

        if (fifobyte_active_e8[i])

          fifo[fiforow_ptr_e8[i]][(i*8) +: 8] <= fifodata_e8[(i*8) +: 8];

     end

    endgenerate

The error message is below :

[Synth 8-2913] Unsupported Dual Port Block Ram Template for fifo_column [23] fifo_reg 

Is there any probelm with the coding style ?

Or I should set any special option for it .

My vivado version is 2017.1_AR69152 

 

Thanks in advance

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Xilinx Employee
Xilinx Employee
1,004 Views
Registered: ‎05-14-2008

gtliu@faraday-tech.com wrote:

Thanks for your reply.

I have set its ram style to "register" instead of "block" or "distributed".

Problem will be solved.

But I am not sure the difference between these ram style.

 


There are some dedicated resources in FPGA to implement memory, such as Block RAM, distributed RAM (LUTRAM).

In general Block RAM gives the best performance (not in all cases of course). For more details about RAM resource, please refer to the "Memory Resources User Guide" of your target device family.

ram_style = "block" means using Block RAM, "distributed" means using LUTRAM, and "registers" means using the fabric CLB resources (LUT+registers) instead of dedicated RAM. We usually choose "registers" for small memories.

Loop is not supported for RAM inference. So avoid using loop to describe your memory. You can refer to the language template that yangc mentioned for how to write the code so that Vivado can infer block RAM. I'm afraid ram_style="registers" is not really what you want.

-vivian

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Xilinx Employee
Xilinx Employee
1,060 Views
Registered: ‎02-27-2019

Hi gtliu@faraday-tech.com ,

   If you want to generate RAM as BRAM , it's a good way to refer to Language Templates in vivado GUI .  For example ,Language Templates->Verilog->Synthesis Constructs->Coding Examples->RAM->BlockRAM.  If you want to code by yourself , may be it can't meet the behavior of the BRAM and tool would report the errors.

Yang

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Don't forget to reply, kudo, and accept as solution.
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Highlighted
1,016 Views
Registered: ‎06-26-2019

Thanks for your reply.

I have set its ram style to "register" instead of "block" or "distributed".

Problem will be solved.

But I am not sure the difference between these ram style.

 

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
1,005 Views
Registered: ‎05-14-2008

gtliu@faraday-tech.com wrote:

Thanks for your reply.

I have set its ram style to "register" instead of "block" or "distributed".

Problem will be solved.

But I am not sure the difference between these ram style.

 


There are some dedicated resources in FPGA to implement memory, such as Block RAM, distributed RAM (LUTRAM).

In general Block RAM gives the best performance (not in all cases of course). For more details about RAM resource, please refer to the "Memory Resources User Guide" of your target device family.

ram_style = "block" means using Block RAM, "distributed" means using LUTRAM, and "registers" means using the fabric CLB resources (LUT+registers) instead of dedicated RAM. We usually choose "registers" for small memories.

Loop is not supported for RAM inference. So avoid using loop to describe your memory. You can refer to the language template that yangc mentioned for how to write the code so that Vivado can infer block RAM. I'm afraid ram_style="registers" is not really what you want.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------

View solution in original post