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2U3
Adventurer
Adventurer
296 Views
Registered: ‎05-25-2020

Using module to fail in SystemVerilog

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Hello,

It works well with a code in "CASE 1" shown below, during button being pressed LED is on, but "CASE 2."

Could anyone please show me why and how to correct?

Thank you.

 

================================================ CASE 1

`timescale 1ns / 1ps
//---------------------------------------
// btn_led.sv
// Create Date: 12/30/2020 01:39:00 AM
//---------------------------------------
module btn_led (
input logic IN_CLK, IN_BTN,
output logic OUT_LED
);
reg led = 1'd1;
assign OUT_LED = led;

reg xxx = 1'd0;
always @(posedge IN_CLK) begin
if (IN_BTN) begin
led <= 1'd0;
end else begin
led <= 1'd1;
end
end
/*
*/

btn_led_sub # (
.CNT_X(868))
ser (
.IN_CLK(IN_CLK),
.IN_BTN(IN_BTN),
.OUT_LED(xxx));
//.OUT_LED(led));

endmodule

================================================ CASE 1 (END)

 


================================================ CASE 2

`timescale 1ns / 1ps
//---------------------------------------
// btn_led.sv
// Create Date: 12/30/2020 01:39:00 AM
//---------------------------------------
module btn_led (
input logic IN_CLK, IN_BTN,
output logic OUT_LED
);
reg led = 1'd1;
assign OUT_LED = led;

/*
reg xxx = 1'd0;
always @(posedge IN_CLK) begin
if (IN_BTN) begin
led <= 1'd0;
end else begin
led <= 1'd1;
end
end
*/

btn_led_sub # (
.CNT_X(868))
ser (
.IN_CLK(IN_CLK),
.IN_BTN(IN_BTN),
//.OUT_LED(xxx));
.OUT_LED(led));

endmodule

================================================ CASE 2 (END)

 


`timescale 1ns / 1ps
//---------------------------------------
// btn_led_sub.sv
// Create Date: 12/30/2020 01:49:22 AM
//---------------------------------------
module btn_led_sub(
input logic IN_CLK, IN_BTN,
output logic OUT_LED
);

parameter CNT_X = 32'd124999999; // 125MHz clk for 1sec
reg led = 1'd1;

assign OUT_LED = led;

always @(posedge IN_CLK) begin
if (IN_BTN) begin
led <= 1'd0;
end else begin
led <= 1'd1;
end
end

endmodule

 

 

 

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viviany
Xilinx Employee
Xilinx Employee
243 Views
Registered: ‎05-14-2008

What problem do you have with Case2?

I see a mistake in the code for case2.

You should remove this line in btn_led module:

reg led = 1'd1;

-vivian

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-------------------------------------------------------------------------------------------------

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2 Replies
viviany
Xilinx Employee
Xilinx Employee
244 Views
Registered: ‎05-14-2008

What problem do you have with Case2?

I see a mistake in the code for case2.

You should remove this line in btn_led module:

reg led = 1'd1;

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------

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2U3
Adventurer
Adventurer
226 Views
Registered: ‎05-25-2020

The problem was that during a button being pressed an LED is still off in case 2, while an LED is on in case 1.

Then, removing the line makes the LED being on in case 2, it is behavior being intended.

Thank you for very helpful answer.

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