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Adventurer
Adventurer
359 Views
Registered: ‎07-14-2015

VHDL : Array of unsigned - Synth error

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Hi,

In my VHDL code, when I declare an unsigned array type, it conflicts with an overloaded operator in the numeric_std. 

my doubt is: Why does the type declaration affect the operator overloading? Code is given below. Any help is very much appreciated.

Synth Error: 

ERROR: [Synth 8-944] 2 definitions of operator "&" match here [C:/my_files/vivado/project_1/project_1.srcs/sources_1/new/test_numeric.vhd:21]
INFO: [Synth 8-1047] first match for '"&"' found here [./2008/src/numeric_std_2008.vhd:81]
INFO: [Synth 8-1047] another match for '"&"' found here [C:/my_files/vivado/project_1/project_1.srcs/sources_1/new/test_numeric.vhd:15]

Code :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity test_numeric is
  port(
    input1  : in  unsigned(9 downto 0);
    output1 : out unsigned(13 downto 0)
    );
end test_numeric;

architecture Behavioral of test_numeric is

  signal Ones : unsigned(31 downto 0);  -- used to get unsigned MAX arrays
  type RRUnsignedArrayTp is array ( 0 to 3) of unsigned(31 downto 0);
  --signal test : RRUnsignedArrayTp(0 to 3)(31 downto 0);

begin

  Ones    <= (others => '1');
  output1 <= unsigned('0' & input1 & Ones(2 downto 0));

end Behavioral;

 

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Scholar richardhead
Scholar
279 Views
Registered: ‎08-01-2012

Re: VHDL : Array of unsigned - Synth error

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Because you made a new type that is an array of unsigned, the compiler doesnt know if your concatenation is to make an unsigned value or an array of unsigned (you RRUnsignedArrayTp type)

you need to qualify to the compiler what you mean with the qualifier mark (') :

output1 <= unsigned'('0' & input1 & Ones(2 downto 0));

View solution in original post

7 Replies
352 Views
Registered: ‎06-21-2017

Re: VHDL : Array of unsigned - Synth error

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Input1 is 10 bits.  Output1 is 11 bits.  In the statement where you are assigning a value to output1, you are concatinating 14 bits. 

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Adventurer
Adventurer
348 Views
Registered: ‎07-14-2015

Re: VHDL : Array of unsigned - Synth error

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Hi @bruce_karaffa 

Thank you for the reply.

 

That was a mistake while posting. I was doing multiple experiments with the concat. Corrected the output bit length. The error mentioned in the original post will occur now.

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Scholar drjohnsmith
Scholar
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Registered: ‎07-09-2009

Re: VHDL : Array of unsigned - Synth error

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I cant try at the moment,

two thoughts

a) try using the resize operator

b) try unsigned('0') & fred & george ;

 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Adventurer
Adventurer
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Registered: ‎07-14-2015

Re: VHDL : Array of unsigned - Synth error

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The problem is how the operator "&" is defined in the statement "type RRUnsignedArrayTp is array ( 0 to 3) of unsigned(31 downto 0);"?
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Scholar richardhead
Scholar
280 Views
Registered: ‎08-01-2012

Re: VHDL : Array of unsigned - Synth error

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Because you made a new type that is an array of unsigned, the compiler doesnt know if your concatenation is to make an unsigned value or an array of unsigned (you RRUnsignedArrayTp type)

you need to qualify to the compiler what you mean with the qualifier mark (') :

output1 <= unsigned'('0' & input1 & Ones(2 downto 0));

View solution in original post

Adventurer
Adventurer
209 Views
Registered: ‎07-14-2015

Re: VHDL : Array of unsigned - Synth error

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@richardhead 

Thank you for your reply.

Are you saying that the concat of two unsigned numbers forms the array defined as the type? But this error doesn't appear when the type is not defined.

As per  1076-2008 LRM: 9.2.5. 

subtype BYTE is BIT_VECTOR (7 downto 0);
type MEMORY is array (Natural range <>) of BYTE;
-- The following concatenation accepts two BIT_VECTORs and returns
-- a BIT_VECTOR [case a)]:
constant ZERO: BYTE := "0000" & "0000";
-- The next two examples show that the same expression can represent
-- either case a) or case c), depending on the context of
-- the expression.
-- The following concatenation accepts two BIT_VECTORS and returns
-- a BIT_VECTOR [case a)]:
constant C1: BIT_VECTOR := ZERO & ZERO;

 

Here, two concat BIT_VECTORS of two bit vectors result in  a bit vector itself, not the memory type. Using this idea, I changed the code. I Kind of understood how it does. 

 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity test_numeric is
  port(
    input1  : in  unsigned(9 downto 0);
    output1 : out unsigned(13 downto 0)
    );
end test_numeric;

architecture Behavioral of test_numeric is

  signal Ones : unsigned(31 downto 0);  -- used to get unsigned MAX arrays
  type RRUnsignedArrayTp is array ( 0 to 3) of unsigned(31 downto 0);
  signal s_out : unsigned(13 downto 0);
    
begin

  Ones    <= (others => '1');
  s_out <= '0' & input1 & Ones(2 downto 0);
  output1 <= unsigned(s_out);

end Behavioral;

 

 

@drjohnsmith , I used resize 

output1 <= unsigned(resize(('0' & input1 & Ones(2 downto 0)),14));.

 I don't know if you meant the same. But this also works. Thank you.

 

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Scholar richardhead
Scholar
203 Views
Registered: ‎08-01-2012

Re: VHDL : Array of unsigned - Synth error

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@rakend.r 

There is no array of unsigned type defined in any standard libraries. So when you just do this:

signal a,b : unsigned(7 downto 0);
signal c : unsigned(15 downto 0);

c <= a&b;

It knows what to do because unsigned is the only option available.

When you have another type defined, it doesnt know whether you want an array type or an unsigned type, so sometimes you need to qualify exactly what you mean.