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VHDL - Hierarchical reference

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Explorer
Posts: 156
Registered: ‎04-01-2016
Accepted Solution

VHDL - Hierarchical reference

Hi all,

 

in VHDL2008 there was added hierarchical names for use in testbenches: Hierarchical Names [Doulos]

I really like this feature for use in testbenches because signals can be traced.

 

Now my project leader wants to know if this is working for Synthesis in the Vivado toolchain as well (for reading and writing some signals). Background is that we use an flow from another team and need some signals which aren't ports and we cannot modify that code so easily.

 

Even if this would be the simplest and fastest way I hope - to be honest - that this feature is not available for synthesis. Even if it would be the simplest solution for our current problem I really don't want to to this because I know how ugly and bad this coding style would be.

 

So please don't judge me for that question because I would hate that possibility as well but for the sake of completeness I have to ask that question. :)

 

Kind regards

Sebastian


Accepted Solutions
Scholar
Posts: 876
Registered: ‎08-07-2014

Re: VHDL - Hierarchical reference

[ Edited ]

@richardhead,

 

I only referred to the synth guide because the OP asked a Q about the synth ability of that feature.

 

May be I should have written - I didn't find it there too, so I assume that feature is not support by Vivado for synthesis.

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Scholar
Posts: 876
Registered: ‎08-07-2014

Re: VHDL - Hierarchical reference

@sebastian_z,

 

have you referred to the https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug901-vivado-synthesis.pdf Synthesis Guide?

 

See Chapter-6 for VHDL2008 supported features.

 

Now my project leader wants to know if this is working for Synthesis in the Vivado toolchain as well (for reading and writing some signals).

Wait a minute, as I understand it, this is a test-bench feature!

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FPGA enthusiast!
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Explorer
Posts: 156
Registered: ‎04-01-2016

Re: VHDL - Hierarchical reference

Hi @dpaul24

 

thank you very much for your answer. In that document I just found something about hierarchical names in the Verilog / SystemVerilog section.

 

So I assume that feature is even unsupported for testbenches in the ISim. Perhaps anyone could confirm that?

 

Thanks in advance!

Sebastian

 

Scholar
Posts: 876
Registered: ‎08-07-2014

Re: VHDL - Hierarchical reference

I didn't find it there too, so I assume that feature is not support by Vivado.

 

 

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Highlighted
Voyager
Posts: 332
Registered: ‎08-01-2012

Re: VHDL - Hierarchical reference

External Names (the official VHDL term) is supported in Vivado simulation:

 

Xilinx refer to it as "Hierarchical references to signal"

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug900-vivado-logic-simulation.pdf

 

Dont expect synthesis support any time soon

@dpaul24 No feature of VHDL is proscribed only for simulation or synthesis. Vendors chose what features they want to support, and alot of VHDL is currently simulation only (and unlikely to ever be useable in a synthesisor).

Scholar
Posts: 876
Registered: ‎08-07-2014

Re: VHDL - Hierarchical reference

[ Edited ]

@richardhead,

 

I only referred to the synth guide because the OP asked a Q about the synth ability of that feature.

 

May be I should have written - I didn't find it there too, so I assume that feature is not support by Vivado for synthesis.

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FPGA enthusiast!
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Voyager
Posts: 287
Registered: ‎04-26-2012

Re: VHDL - Hierarchical reference

@sebastian_z  "Now my project leader wants to know if this is working for Synthesis in the Vivado toolchain as well (for reading and writing some signals)."

 

For what it's worth, Xilinx has previously declared that Vivado Synthesis will not support global signals in packages (which could be used similarly to the new 2008 hierarchical references for probing in testbenches without plumbing signals though ports)

 

  AR# 65848  Will Vivado Synthesis support global signals in VHDL? (signals declared in a package)
  https://www.xilinx.com/support/answers/65848.html

 

-Brian

 

https://forums.xilinx.com/t5/Synthesis/Using-VHDL-global-signals-signals-declared-in-a-package/td-p/495356

https://forums.xilinx.com/t5/Synthesis/XST-Detected-unknown-constraint-property-quot-package-net-quot/m-p/365349#M9138

 

Explorer
Posts: 156
Registered: ‎04-01-2016

Re: VHDL - Hierarchical reference

Hi @brimdavis

 

cool. That sounds good. So we have to find another and - most of all - better solution. :)

 

Kind regards

Sebastian

Voyager
Posts: 332
Registered: ‎08-01-2012

Re: VHDL - Hierarchical reference

@sebastian_z

 

I think you misread @brimdavis post. Xilinx have said they WILL NOT support global signals (and neither will Altera/Intel)

Explorer
Posts: 156
Registered: ‎04-01-2016

Re: VHDL - Hierarchical reference

Hi @richardhead

 

I think I understood correctly. :)

I like that they don't support that features because it will lead to very bad code which nobody will ever be able to debug. So I like that I can tell my project leader that we have to do it in a proper way which will be more work but will lead to better code. :)

 

Kind regards

Sebastian