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richardhead
Scholar
Scholar
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Registered: ‎08-01-2012

[VHDL2019 Feature Request] Interfaces

VHDL 2019 adds Interfaces, similar to interfaces and modports in SV, which are already supported.

An example of a VHDL 2019 Interface is:

 

-- A FIFO like streaming interface:
type StreamingIf is record
  Valid  : Std_uLogic;
  Data   : Std_uLogic_Vector(7 downto 0);
  Ack    : Std_uLogic;
end record StreamingIf;

view MasterView of StreamingIf is
   Valid : out;
   Data  : out;
   Ack   : in;
end view MasterView;

alias SlaveView is MasterView'CONVERSE;
-- Equivalent mode view declaration
-- view SlaveView of MasterView is
--    Valid : in;
--    Data  : in;
--    Ack   : out;
-- end view SlaveView;

-- A stream processing element
entity SPE is
  port (
    Clock  : in   Std_uLogic;
    Reset  : in   Std_uLogic;
    Input  : view SlaveView;   -- input from previous SPE
    Output : view MasterView   -- output to next SPE
  );
end entity;

 

 

And then, port mapping can simply be done like this:

 

signal loopback_connect : StreamingIf;
...
inst : entity work.SPE 
port map (
  Clock => Clock,
  Reset => Reset,
  Input => loopback_connect,
  Output => loopback_connect
);
  

 

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